Support 3D Custom Switch Blocks

libs/libarchfpga/src/parse_switchblocks.cpp

@@ -65,6 +65,9 @@ static void parse_comma_separated_wire_points(const char* ch, std::vector<t_wire
 /* Parses the number of connections type */
 static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn);
 
+/* Set connection from_side and to_side for custom switch block pattern*/
+static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type);
+
 /* parse switch_override in wireconn */
 static void parse_switch_override(const char* switch_override, t_wireconn_inf& wireconn, const t_arch_switch_inf* switches, int num_switches);
 
@@ -269,6 +272,70 @@ static void parse_num_conns(std::string num_conns, t_wireconn_inf& wireconn) {
     wireconn.num_conns_formula = num_conns;
 }
 
+//set sides for a specific conn for custom switch block pattern
+static void set_switch_func_type(SB_Side_Connection& conn, const char* func_type) {
+    if (0 == strcmp(func_type, "lt")) {
+        conn.set_sides(LEFT, TOP);
+    } else if (0 == strcmp(func_type, "lr")) {
+        conn.set_sides(LEFT, RIGHT);
+    } else if (0 == strcmp(func_type, "lb")) {
+        conn.set_sides(LEFT, BOTTOM);
+    } else if (0 == strcmp(func_type, "la")) {
+        conn.set_sides(LEFT, ABOVE);
+    } else if (0 == strcmp(func_type, "lu")) {
+        conn.set_sides(LEFT, UNDER);
+    } else if (0 == strcmp(func_type, "tl")) {
+        conn.set_sides(TOP, LEFT);
+    } else if (0 == strcmp(func_type, "tb")) {
+        conn.set_sides(TOP, BOTTOM);
+    } else if (0 == strcmp(func_type, "tr")) {
+        conn.set_sides(TOP, RIGHT);
+    } else if (0 == strcmp(func_type, "ta")) {
+        conn.set_sides(TOP, ABOVE);
+    } else if (0 == strcmp(func_type, "tu")) {
+        conn.set_sides(TOP, UNDER);
+    } else if (0 == strcmp(func_type, "rt")) {
+        conn.set_sides(RIGHT, TOP);
+    } else if (0 == strcmp(func_type, "rl")) {
+        conn.set_sides(RIGHT, LEFT);
+    } else if (0 == strcmp(func_type, "rb")) {
+        conn.set_sides(RIGHT, BOTTOM);
+    } else if (0 == strcmp(func_type, "ra")) {
+        conn.set_sides(RIGHT, ABOVE);
+    } else if (0 == strcmp(func_type, "ru")) {
+        conn.set_sides(RIGHT, UNDER);
+    } else if (0 == strcmp(func_type, "bl")) {
+        conn.set_sides(BOTTOM, LEFT);
+    } else if (0 == strcmp(func_type, "bt")) {
+        conn.set_sides(BOTTOM, TOP);
+    } else if (0 == strcmp(func_type, "br")) {
+        conn.set_sides(BOTTOM, RIGHT);
+    } else if (0 == strcmp(func_type, "ba")) {
+        conn.set_sides(BOTTOM, ABOVE);
+    } else if (0 == strcmp(func_type, "bu")) {
+        conn.set_sides(BOTTOM, UNDER);
+    } else if (0 == strcmp(func_type, "al")) {
+        conn.set_sides(ABOVE, LEFT);
+    } else if (0 == strcmp(func_type, "at")) {
+        conn.set_sides(ABOVE, TOP);
+    } else if (0 == strcmp(func_type, "ar")) {
+        conn.set_sides(ABOVE, RIGHT);
+    } else if (0 == strcmp(func_type, "ab")) {
+        conn.set_sides(ABOVE, BOTTOM);
+    } else if (0 == strcmp(func_type, "ul")) {
+        conn.set_sides(UNDER, LEFT);
+    } else if (0 == strcmp(func_type, "ut")) {
+        conn.set_sides(UNDER, TOP);
+    } else if (0 == strcmp(func_type, "ur")) {
+        conn.set_sides(UNDER, RIGHT);
+    } else if (0 == strcmp(func_type, "ub")) {
+        conn.set_sides(UNDER, BOTTOM);
+    } else {
+        /* unknown permutation function */
+        archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified: %s\n", func_type);
+    }
+}
+
 /* Loads permutation funcs specified under Node into t_switchblock_inf. Node should be
  * <switchfuncs> */
 void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiutil::loc_data& loc_data) {
@@ -300,34 +367,8 @@ void read_sb_switchfuncs(pugi::xml_node Node, t_switchblock_inf* sb, const pugiu
         func_formula = get_attribute(SubElem, "formula", loc_data).as_string(nullptr);
 
         /* go through all the possible cases of func_type */
-        if (0 == strcmp(func_type, "lt")) {
-            conn.set_sides(LEFT, TOP);
-        } else if (0 == strcmp(func_type, "lr")) {
-            conn.set_sides(LEFT, RIGHT);
-        } else if (0 == strcmp(func_type, "lb")) {
-            conn.set_sides(LEFT, BOTTOM);
-        } else if (0 == strcmp(func_type, "tl")) {
-            conn.set_sides(TOP, LEFT);
-        } else if (0 == strcmp(func_type, "tb")) {
-            conn.set_sides(TOP, BOTTOM);
-        } else if (0 == strcmp(func_type, "tr")) {
-            conn.set_sides(TOP, RIGHT);
-        } else if (0 == strcmp(func_type, "rt")) {
-            conn.set_sides(RIGHT, TOP);
-        } else if (0 == strcmp(func_type, "rl")) {
-            conn.set_sides(RIGHT, LEFT);
-        } else if (0 == strcmp(func_type, "rb")) {
-            conn.set_sides(RIGHT, BOTTOM);
-        } else if (0 == strcmp(func_type, "bl")) {
-            conn.set_sides(BOTTOM, LEFT);
-        } else if (0 == strcmp(func_type, "bt")) {
-            conn.set_sides(BOTTOM, TOP);
-        } else if (0 == strcmp(func_type, "br")) {
-            conn.set_sides(BOTTOM, RIGHT);
-        } else {
-            /* unknown permutation function */
-            archfpga_throw(__FILE__, __LINE__, "Unknown permutation function specified: %s\n", func_type);
-        }
+        set_switch_func_type(conn, func_type);
+
         func_ptr = &(sb->permutation_map[conn]);
 
         /* Here we load the specified switch function(s) */
@@ -404,8 +445,8 @@ static void check_bidir_switchblock(const t_permutation_map* permutation_map) {
     SB_Side_Connection conn;
 
     /* iterate over all combinations of from_side -> to side */
-    for (e_side from_side : {TOP, RIGHT, BOTTOM, LEFT}) {
-        for (e_side to_side : {TOP, RIGHT, BOTTOM, LEFT}) {
+    for (e_side from_side : SIDES) {
+        for (e_side to_side : SIDES) {
             /* can't connect a switchblock side to itself */
             if (from_side == to_side) {
                 continue;

libs/libarchfpga/src/physical_types.h

@@ -175,11 +175,18 @@ enum e_side : unsigned char {
     RIGHT = 1,
     BOTTOM = 2,
     LEFT = 3,
-    NUM_SIDES
+    NUM_SIDES = 4,
+    ABOVE = 5,
+    UNDER = 6,
+    NUM_OF_TOTAL_SIDES,
 };
+
 constexpr std::array<e_side, NUM_SIDES> SIDES = {{TOP, RIGHT, BOTTOM, LEFT}};                    //Set of all side orientations
 constexpr std::array<const char*, NUM_SIDES> SIDE_STRING = {{"TOP", "RIGHT", "BOTTOM", "LEFT"}}; //String versions of side orientations
 
+constexpr std::array<e_side, NUM_OF_TOTAL_SIDES> TOTAL_SIDES = {{TOP, RIGHT, BOTTOM, LEFT, ABOVE, UNDER}};                        //Set of all side orientations including different layers
+constexpr std::array<const char*, NUM_OF_TOTAL_SIDES> TOTAL_SIDE_STRING = {{"TOP", "RIGHT", "BOTTOM", "LEFT", "ABOVE", "UNDER"}}; //String versions of side orientations including different layers
+
 /* pin location distributions */
 enum e_pin_location_distr {
     E_SPREAD_PIN_DISTR,

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -475,7 +475,7 @@ struct ArchReader {
         type.pin_height_offset.resize(type.num_pins, 0);
 
         type.pinloc.resize({1, 1, 4}, std::vector<bool>(type.num_pins, false));
-        for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+        for (e_side side : SIDES) {
             for (int pin = 0; pin < type.num_pins; pin++) {
                 type.pinloc[0][0][side][pin] = true;
                 type.pin_width_offset[pin] = 0;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -501,7 +501,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
         int num_sides = 4 * (type->width * type->height);
         int side_index = 0;
         int count = 0;
-        for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+        for (e_side side : SIDES) {
             for (int width = 0; width < type->width; ++width) {
                 for (int height = 0; height < type->height; ++height) {
                     for (int pin_offset = 0; pin_offset < (type->num_pins / num_sides) + 1; ++pin_offset) {
@@ -526,7 +526,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
         while (ipin < type->num_pins) {
             for (int width = 0; width < type->width; ++width) {
                 for (int height = 0; height < type->height; ++height) {
-                    for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+                    for (e_side side : SIDES) {
                         if (((width == 0 && side == LEFT)
                              || (height == type->height - 1 && side == TOP)
                              || (width == type->width - 1 && side == RIGHT)
@@ -567,7 +567,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
         while (ipin < input_pins.size()) {
             for (int width = 0; width < type->width; ++width) {
                 for (int height = 0; height < type->height; ++height) {
-                    for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+                    for (e_side side : SIDES) {
                         if (ipin < input_pins.size()) {
                             //Pins still to allocate
 
@@ -590,7 +590,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
         while (ipin < output_pins.size()) {
             for (int width = 0; width < type->width; ++width) {
                 for (int height = 0; height < type->height; ++height) {
-                    for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+                    for (e_side side : SIDES) {
                         if (((width == 0 && side == LEFT)
                              || (height == type->height - 1 && side == TOP)
                              || (width == type->width - 1 && side == RIGHT)
@@ -621,7 +621,7 @@ static void LoadPinLoc(pugi::xml_node Locations,
             for (int layer = 0; layer < num_of_avail_layer; ++layer) {
                 for (int width = 0; width < type->width; ++width) {
                     for (int height = 0; height < type->height; ++height) {
-                        for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+                        for (e_side side : SIDES) {
                             for (auto token : pin_locs->assignments[sub_tile_index][width][height][layer][side]) {
                                 auto pin_range = ProcessPinString<t_sub_tile*>(Locations,
                                                                                &sub_tile,
@@ -3398,7 +3398,7 @@ static void ProcessPinLocations(pugi::xml_node Locations,
         for (int l = 0; l < num_of_avail_layer; ++l) {
             for (int w = 0; w < PhysicalTileType->width; ++w) {
                 for (int h = 0; h < PhysicalTileType->height; ++h) {
-                    for (e_side side : {TOP, RIGHT, BOTTOM, LEFT}) {
+                    for (e_side side : SIDES) {
                         for (auto token : pin_locs->assignments[sub_tile_index][w][h][l][side]) {
                             InstPort inst_port(token.c_str());
 

libs/librrgraph/src/base/check_rr_graph.cpp

@@ -485,9 +485,13 @@ void check_rr_node(const RRGraphView& rr_graph,
                 tracks_per_node = ((rr_type == CHANX) ? chan_width.x_list[ylow] : chan_width.y_list[xlow]);
             }
 
-            if (ptc_num >= nodes_per_chan) {
-                VPR_ERROR(VPR_ERROR_ROUTE,
-                          "in check_rr_node: inode %d (type %d) has a ptc_num of %d.\n", inode, rr_type, ptc_num);
+            //if a chanx/chany has length 0, it means it is used to connect different dice together
+            //hence, the ptc number can be larger than nodes_per_chan
+            if(xlow != xhigh || ylow != yhigh) {
+                if (ptc_num >= nodes_per_chan) {
+                    VPR_ERROR(VPR_ERROR_ROUTE,
+                              "in check_rr_node: inode %d (type %d) has a ptc_num of %d.\n", inode, rr_type, ptc_num);
+                }
             }
 
             if (capacity != tracks_per_node) {

libs/librrgraph/src/base/rr_rc_data.cpp

@@ -17,7 +17,7 @@ short find_create_rr_rc_data(const float R, const float C, std::vector<t_rr_rc_d
                             match);
 
     if (itr == rr_rc_data.end()) {
-        //Note found -> create it
+        //Not found -> create it
         rr_rc_data.emplace_back(R, C);
 
         itr = --rr_rc_data.end(); //Iterator to inserted value

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: aad09e42e426be6012c2f65ddb636cd0
  */
 
 #include <functional>
@@ -1577,7 +1577,7 @@ template<std::size_t N>
 constexpr const char *lookup_switch_type[] = {"UXSD_INVALID", "mux", "tristate", "pass_gate", "short", "buffer"};
 constexpr const char *lookup_pin_type[] = {"UXSD_INVALID", "OPEN", "OUTPUT", "INPUT"};
 constexpr const char *lookup_node_type[] = {"UXSD_INVALID", "CHANX", "CHANY", "SOURCE", "SINK", "OPIN", "IPIN"};
-constexpr const char *lookup_node_direction[] = {"UXSD_INVALID", "INC_DIR", "DEC_DIR", "BI_DIR"};
+constexpr const char *lookup_node_direction[] = {"UXSD_INVALID", "INC_DIR", "DEC_DIR", "BI_DIR", "NONE"};
 constexpr const char *lookup_loc_side[] = {"UXSD_INVALID", "LEFT", "RIGHT", "TOP", "BOTTOM", "RIGHT_LEFT", "RIGHT_BOTTOM", "RIGHT_BOTTOM_LEFT", "TOP_RIGHT", "TOP_BOTTOM", "TOP_LEFT", "TOP_RIGHT_BOTTOM", "TOP_RIGHT_LEFT", "TOP_BOTTOM_LEFT", "TOP_RIGHT_BOTTOM_LEFT", "BOTTOM_LEFT"};
 
 /* Lexers(string->token functions) for enums. */
@@ -1771,6 +1771,14 @@ inline enum_node_type lex_enum_node_type(const char *in, bool throw_on_invalid,
 inline enum_node_direction lex_enum_node_direction(const char *in, bool throw_on_invalid, const std::function<void(const char *)> * report_error){
 	unsigned int len = strlen(in);
 	switch(len){
+	case 4:
+		switch(*((triehash_uu32*)&in[0])){
+		case onechar('N', 0, 32) | onechar('O', 8, 32) | onechar('N', 16, 32) | onechar('E', 24, 32):
+			return enum_node_direction::NONE;
+		break;
+		default: break;
+		}
+		break;
 	case 6:
 		switch(*((triehash_uu32*)&in[0])){
 		case onechar('B', 0, 32) | onechar('I', 8, 32) | onechar('_', 16, 32) | onechar('D', 24, 32):

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_capnp.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42
+ * Cmdline: uxsdcxx/uxsdcap.py /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: aad09e42e426be6012c2f65ddb636cd0
  */
 
 #include <functional>
@@ -238,6 +238,8 @@ inline enum_node_direction conv_enum_node_direction(ucap::NodeDirection e, const
 		return enum_node_direction::DEC_DIR;
 	case ucap::NodeDirection::BI_DIR:
 		return enum_node_direction::BI_DIR;
+	case ucap::NodeDirection::NONE:
+		return enum_node_direction::NONE;
 	default:
 		(*report_error)("Unknown enum_node_direction");
 		throw std::runtime_error("Unreachable!");
@@ -254,6 +256,8 @@ inline ucap::NodeDirection conv_to_enum_node_direction(enum_node_direction e) {
 		return ucap::NodeDirection::DEC_DIR;
 	case enum_node_direction::BI_DIR:
 		return ucap::NodeDirection::BI_DIR;
+	case enum_node_direction::NONE:
+		return ucap::NodeDirection::NONE;
 	default:
 		throw std::runtime_error("Unknown enum_node_direction");
 	}

libs/librrgraph/src/io/gen/rr_graph_uxsdcxx_interface.h

@@ -4,9 +4,9 @@
  * https://github.com/duck2/uxsdcxx
  * Modify only if your build process doesn't involve regenerating this file.
  *
- * Cmdline: uxsdcxx/uxsdcxx.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
- * md5sum of input file: bf49388f038e0d0e4a12403ebb964b42
+ * Cmdline: uxsdcxx/uxsdcxx.py /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * Input file: /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+ * md5sum of input file: aad09e42e426be6012c2f65ddb636cd0
  */
 
 #include <functional>
@@ -27,7 +27,7 @@ enum class enum_pin_type {UXSD_INVALID = 0, OPEN, OUTPUT, INPUT};
 
 enum class enum_node_type {UXSD_INVALID = 0, CHANX, CHANY, SOURCE, SINK, OPIN, IPIN};
 
-enum class enum_node_direction {UXSD_INVALID = 0, INC_DIR, DEC_DIR, BI_DIR};
+enum class enum_node_direction {UXSD_INVALID = 0, INC_DIR, DEC_DIR, BI_DIR, NONE};
 
 enum class enum_loc_side {UXSD_INVALID = 0, LEFT, RIGHT, TOP, BOTTOM, RIGHT_LEFT, RIGHT_BOTTOM, RIGHT_BOTTOM_LEFT, TOP_RIGHT, TOP_BOTTOM, TOP_LEFT, TOP_RIGHT_BOTTOM, TOP_RIGHT_LEFT, TOP_BOTTOM_LEFT, TOP_RIGHT_BOTTOM_LEFT, BOTTOM_LEFT};
 

libs/librrgraph/src/io/rr_graph.xsd

@@ -232,6 +232,7 @@
       <xs:enumeration value="INC_DIR"/>
       <xs:enumeration value="DEC_DIR"/>
       <xs:enumeration value="BI_DIR"/>
+      <xs:enumeration value="NONE"/>
     </xs:restriction>
   </xs:simpleType>
 

libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h

@@ -1883,6 +1883,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
                 return Direction::DEC;
             case uxsd::enum_node_direction::BI_DIR:
                 return Direction::BIDIR;
+            case uxsd::enum_node_direction::NONE:
+                return Direction::NONE;
             default:
                 report_error(
                     "Invalid node direction %d", direction);
@@ -1897,6 +1899,8 @@ class RrGraphSerializer final : public uxsd::RrGraphBase<RrGraphContextTypes> {
                 return uxsd::enum_node_direction::DEC_DIR;
             case Direction::BIDIR:
                 return uxsd::enum_node_direction::BI_DIR;
+            case Direction::NONE:
+                return uxsd::enum_node_direction::NONE;
             default:
                 report_error(
                     "Invalid direction %d", direction);

libs/librrgraph/src/utils/describe_rr_node.cpp

@@ -11,7 +11,6 @@ std::string describe_rr_node(const RRGraphView& rr_graph,
                              bool is_flat) {
 
     std::string msg = vtr::string_fmt("RR node: %d", inode);
-
     if (rr_graph.node_type(inode) == CHANX || rr_graph.node_type(inode) == CHANY) {
         auto cost_index = rr_graph.node_cost_index(inode);
 

libs/libvtrcapnproto/gen/rr_graph_uxsdcxx.capnp

@@ -2,11 +2,11 @@
 # https://github.com/duck2/uxsdcxx
 # Modify only if your build process doesn't involve regenerating this file.
 #
-# Cmdline: uxsdcxx/uxsdcap.py /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
-# Input file: /home/smahmoudi/Desktop/vtr/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
-# md5sum of input file: bf49388f038e0d0e4a12403ebb964b42
+# Cmdline: uxsdcxx/uxsdcap.py /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+# Input file: /home/sara/Desktop/rr_3d/vtr-verilog-to-routing/libs/librrgraph/src/io/rr_graph.xsd
+# md5sum of input file: aad09e42e426be6012c2f65ddb636cd0
 
-@0xf7009c96d0510b05;
+@0x8112499188102de5;
 using Cxx = import "/capnp/c++.capnp";
 $Cxx.namespace("ucap");
 
@@ -41,6 +41,7 @@ enum NodeDirection {
 	incDir @1;
 	decDir @2;
 	biDir @3;
+	none @4;
 }
 
 enum LocSide {

vpr/src/pack/post_routing_pb_pin_fixup.cpp

@@ -107,7 +107,7 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li
      * Deposit all the sides
      */
     if (wanted_sides.empty()) {
-        for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) {
+        for (e_side side : SIDES) {
             wanted_sides.push_back(side);
         }
     }