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Merged
merged 168 commits into from
Jun 29, 2023
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8d26d0c
pass number of dice (layers) to t_annealing_state
amin1377 Feb 24, 2023
c1bbb6c
Merge branch 'grid_3d' of https://github.com/verilog-to-routing/vtr-v…
amin1377 Feb 24, 2023
f432606
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Mar 2, 2023
c38a158
add layer_num to t_pl_loc - minor debugging
amin1377 Mar 2, 2023
87d283e
remove max_width.. from device_grid - set layer num to zero
amin1377 Mar 6, 2023
92698c7
adapt find_to_loc_uniform to 3d grid - minimal change to compressed_grid
amin1377 Mar 6, 2023
9552620
add grid_x_to_cx_approx to compressed_grid
amin1377 Mar 7, 2023
f191bce
adapt find_to_loc_centroid to 3d
amin1377 Mar 7, 2023
33ab4da
debug: compressed_grid.h
amin1377 Mar 7, 2023
db8bb85
adapt find_to_loc_median to 3d
amin1377 Mar 7, 2023
91949d9
remove cx_from and cy_from from find_to_loc_median
amin1377 Mar 7, 2023
79f36d0
remove min/max_cx/cy from find_to_loc_centroid
amin1377 Mar 7, 2023
6a55de0
remove t_compressed_loc and use t_type_loc instead
amin1377 Mar 7, 2023
03e5c7a
add layer_num to t_type_loc
amin1377 Mar 7, 2023
7b4311d
use search_range in find_compatible_compressed_loc_in_range - remove …
amin1377 Mar 7, 2023
f6a1561
adapt find_cetroid_neighbor to new changes
amin1377 Mar 8, 2023
7b21d58
refactor and debug initial_placement:init_blk_types_empty_locations
amin1377 Mar 8, 2023
8138000
refactor try_exhaustive_placement - add compatible_sub_tile_num to co…
amin1377 Mar 8, 2023
f3cfaa8
refactor try_random_placement - add get_layer_nums to compressed_grid
amin1377 Mar 8, 2023
3a5e5ad
refactor intersect_range_limit_with_floorplan_constraints with search…
amin1377 Mar 8, 2023
0c40035
minor debugging - add assertion to t_search_range constructor
amin1377 Mar 8, 2023
f484268
abstract away grid in compressed_grid
amin1377 Mar 8, 2023
ad2e608
abstract away compatible_sub_tiles_for_tile in compressed_grid
amin1377 Mar 8, 2023
3786152
make the data members of compressed_grid 3d
amin1377 Mar 8, 2023
cc128d4
minor debugging
amin1377 Mar 8, 2023
3606ee3
resize x_locs and y_locs in create_compressed_block_grid - debug
amin1377 Mar 8, 2023
eb81454
debug: add a condition in find_compatible_compressed_loc_in_range to …
amin1377 Mar 9, 2023
833bf5e
Put back the if block that enlarge the search_range in find_compatibl…
amin1377 Mar 15, 2023
7fd6bd3
remove the newly added if condition in find_compatible_compressed_loc…
amin1377 Mar 15, 2023
a871f34
merge with grid_3d
amin1377 Mar 16, 2023
96f41d8
pass t_physical_tile_loc to grid instead of x,y,layer
amin1377 Mar 16, 2023
481f224
make format
amin1377 Mar 16, 2023
3c823e7
debug cut_spreader - caused due to new changes in grid helper functio…
amin1377 Mar 16, 2023
332e395
restric get_compressed_grid_bounded_search_range to only return searc…
amin1377 Mar 20, 2023
9ed694e
create a new class: GridBlock - encapsulate the grid_block data struc…
amin1377 Mar 21, 2023
fc8f50d
set layer_from to to_layer in find_centroid_neighbor
amin1377 Mar 21, 2023
97572df
make format
amin1377 Mar 21, 2023
4932c08
add layer_num to the place file read/written
amin1377 Mar 21, 2023
8489b4f
adapt cut_spreader to new grid_block
amin1377 Mar 21, 2023
a8617f1
make foramt
amin1377 Mar 21, 2023
ea32bf9
minor debugging
amin1377 Mar 21, 2023
c3c713c
merge with modeling_multi_die_stack
amin1377 Mar 22, 2023
c393411
make format
amin1377 Mar 22, 2023
0c13c0b
print layer_num in CheckGrid
amin1377 Mar 22, 2023
88265b6
merge with modeling_multi_die_stack
amin1377 Mar 23, 2023
c479fce
make format
amin1377 Mar 23, 2023
b16f2e4
initial placement randomly choose a layers among compatible layers
amin1377 Mar 23, 2023
f8651db
pass t_physical_tile_loc to get_coordinate_of_pin - adapt is_loc_on_c…
amin1377 Mar 23, 2023
5f8cd8a
show layer num for placement errors
amin1377 Mar 23, 2023
0f79063
debug: use layer_num to increase usage in commit_move_blocks
amin1377 Mar 23, 2023
1704110
go over all layers in try_exhaustive_placement - Fix the callers of f…
amin1377 Mar 23, 2023
6a11f8e
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Mar 28, 2023
a0cffc2
minor debugging noc_place_utils.cpp
amin1377 Mar 28, 2023
eca910f
region.h: change get_region_rect and set_region_rect to return/accept…
amin1377 Mar 29, 2023
4807cca
minor debugging: cut_spreader.cpp
amin1377 Mar 29, 2023
449ebeb
make GridTileLookup 3D
amin1377 Mar 29, 2023
94ba7b0
remove the default value for layer_num of DeviceGrid:num_instances - …
amin1377 Mar 29, 2023
6398c45
minor debugging - CriticalUniformMoveGenerator propose_move
amin1377 Apr 3, 2023
eaba660
add layer_num parameter to comput method of router lookahead
amin1377 Apr 3, 2023
707b2da
pass layer_num when get_physical_type is called if layer_num is avail…
amin1377 Apr 3, 2023
045cf2c
minor debugging
amin1377 Apr 3, 2023
086a16a
solve the bug with the parameters of grid_blocks.block_at_location
amin1377 Apr 4, 2023
52bb5a2
minor debugging test_setup_noc.cpp
amin1377 Apr 4, 2023
5abb378
add layer_num parameter to PlaceDelayModel.delay() routine
amin1377 Apr 5, 2023
6b2fd6d
change delays_ under DeltaDelayModel to a 3d Matrix to accomodate the…
amin1377 Apr 5, 2023
d502b4c
minor debuggign - make format
amin1377 Apr 5, 2023
dbc6c23
add layer_num 0 to noc test case
amin1377 Apr 5, 2023
e2a4261
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 5, 2023
ac407e2
get the correct dim_size for dump_echo place_delay_model.cpp
amin1377 Apr 5, 2023
5ff1ad6
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 6, 2023
c01cd51
changed t_rr_node_indices to be able to look up for nodes using their…
saaramahmoudi Apr 6, 2023
1d320a6
debug try_exhaustive_placement:if the grid_loc_to_compressed_loc_appr…
amin1377 Apr 6, 2023
49f67be
Forget to fix one find_node call
saaramahmoudi Apr 7, 2023
0ee188e
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
saaramahmoudi Apr 7, 2023
8c4c2a8
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
amin1377 Apr 7, 2023
132ad40
alloc_and_load_rr_node_indicies function has been modified to work wi…
saaramahmoudi Apr 7, 2023
9bb3c7d
change gridBLock and GridTileLookup members from a vector of 2d matri…
amin1377 Apr 7, 2023
219b5f9
alloc_and_load_intra_cluster_rr_node_indices function has been update…
saaramahmoudi Apr 7, 2023
74dbce0
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi Apr 7, 2023
61b4534
added a layer attribute to t_rr_node_data, this increase its size to …
saaramahmoudi Apr 7, 2023
fc38c8b
alloc_and_load_rr_graph_* is modified to consider layer num
saaramahmoudi Apr 7, 2023
39eccb2
most function calls in rr_graph.cpp and rr_graph2.cpp are modified to…
saaramahmoudi Apr 8, 2023
4d736df
debug: correct the end_index parameter called in timing_place_lookup.…
amin1377 Apr 8, 2023
9764a34
fix the assertion for t_pl_loc operations
amin1377 Apr 8, 2023
17486a7
Merge branch 'master' into place_3d
saaramahmoudi Apr 9, 2023
2e3ce5b
fix the test case for deltadelay model
amin1377 Apr 10, 2023
2dde154
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
amin1377 Apr 10, 2023
1aec6c2
remaining functions in the rr_graph2.cpp has been modified to work wi…
saaramahmoudi Apr 10, 2023
f5c25cc
Merge branch 'master' into place_3d
saaramahmoudi Apr 10, 2023
30c60e1
timing_place_lookup.cpp updated to use find_nodes with proper layer_num
saaramahmoudi Apr 10, 2023
cc0bfc5
fixed router_lookahead_map.cpp to work with layer num
saaramahmoudi Apr 10, 2023
8242f77
changed pick_sample_tile function to loop through all the layers
saaramahmoudi Apr 10, 2023
9a9a687
fixed the final function in router_lookahead_map
saaramahmoudi Apr 10, 2023
13d0028
Revert "changed pick_sample_tile function to loop through all the lay…
saaramahmoudi Apr 10, 2023
8505463
bug fixed in pick_sample_tile
saaramahmoudi Apr 10, 2023
7d4111d
fixed rr_graph_uxsdcxx_serializer
saaramahmoudi Apr 10, 2023
acdd436
functions in the clock_network_builders.cpp updated to consider layer…
saaramahmoudi Apr 10, 2023
855cbbc
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi Apr 10, 2023
934e133
pass layer num to computer_router_wire_lookahad
amin1377 Apr 10, 2023
b8da9d1
In exhausitive search in compute_router_wire_lookahead, continue if r…
amin1377 Apr 10, 2023
b6bcbff
router_lookahead_map.cpp:run_dijkstra: Don't expand the node if it is…
amin1377 Apr 10, 2023
a4c93e8
remove the layer_num parameter from compute function router lookahead…
amin1377 Apr 10, 2023
9bc5331
fix dim_size access in router_lookahead_map.cpp: indices needed to be…
amin1377 Apr 11, 2023
9ea3058
set the default value of node's layer_num to zero & add a check in ch…
amin1377 Apr 11, 2023
b8b50e5
remove the default value for layer_num of t_physical_tile_loc struct
amin1377 Apr 11, 2023
ed5e939
cast height and width of grid from size_t to int in rr_graph2.cpp
amin1377 Apr 11, 2023
56fa1a0
debug: timing_place_lookup.cpp:find_direct_connect_sample_locations f…
amin1377 Apr 11, 2023
12e0861
problem with the for iterator in the for loops of timing_place_lookup…
amin1377 Apr 12, 2023
0cc3944
pass layer_num to block_at_loction function called in read_route.cpp:…
amin1377 Apr 12, 2023
86e5469
update graph serializer to accomodate layer num
amin1377 Apr 12, 2023
146257b
sec loc layer in get_blk_type_first_loc
amin1377 Apr 12, 2023
59a1ac9
add assertion to t_pl_loc operations to check layer_num - debug clear…
amin1377 Apr 13, 2023
91ea32f
solve compilation warning caused by comparing int with size_t in cloc…
amin1377 Apr 13, 2023
f1ba697
degub move_utils.cpp:intersect_range_limit_with_floorplan_constraints…
amin1377 Apr 13, 2023
91a5e62
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 17, 2023
3dcc6b0
router_lookahead_map: assert if the from and to layer on different wh…
amin1377 Apr 17, 2023
3f34ccf
Add assertion to "try_place" function to ensure that is_flat is false…
amin1377 Apr 18, 2023
38c99c6
removed the layer attribute from t_rr_node_data and add it to a paral…
saaramahmoudi Apr 18, 2023
99c92bf
Merge branch 'layer_outside_rr_node' into place_3d
saaramahmoudi Apr 18, 2023
ef5e626
Merge branch 'master' into place_3d
saaramahmoudi Apr 18, 2023
b051181
Merge branch 'master' into place_3d
saaramahmoudi Apr 20, 2023
045700a
Merge branch 'master' into place_3d
saaramahmoudi Apr 25, 2023
c9524eb
make format - merge with master
amin1377 May 1, 2023
c6e63bb
print layer num of nodes in .route file
amin1377 May 1, 2023
fe4760d
resolved conflicts with master branch
saaramahmoudi May 11, 2023
81fcfd1
test commit - fix a comment typo
saaramahmoudi May 11, 2023
9023787
Merge branch 'master' into place_3d
saaramahmoudi May 12, 2023
04fe8c8
add some comments about the layer_num in rr_graph_storage.h
amin1377 May 12, 2023
c641102
Add comment on physical tile location under physcial_types.h
amin1377 May 12, 2023
ae22611
Add vpr_3d_noc benchmarks under vtr_reg_nightly_test5
amin1377 May 12, 2023
4c35b5f
add 3d_stratixiv_arch.timing_with_a_embedded_10X10_mesh_noc_topology.…
amin1377 May 12, 2023
8d0c49a
add comment in route_diag/src/main.cpp to emphasize that it doesn't w…
amin1377 May 15, 2023
e69dbb8
update config file of 3d_vpr_noc_star - change 3d noc teste under nig…
amin1377 May 15, 2023
49b7511
fix a typo in vpr_3d_noc_star_topology config file
amin1377 May 16, 2023
a3e5a89
sample 3d-arch minor issue, noc on base die (layer_num = 0) and FPGA …
saaramahmoudi May 18, 2023
b0ae8e5
resolved conflicts with NoC code improvements
saaramahmoudi May 19, 2023
7c4e73f
removed meaningless arch file that was designed for testing layer tag…
saaramahmoudi May 19, 2023
375b62e
moved the actual 3d arch file under arch/multi_die
saaramahmoudi May 19, 2023
2551b3d
added layer num to write_grid_loc in RRGraph
saaramahmoudi May 24, 2023
14689a9
removed debugging extra variables in write_rr_graph
saaramahmoudi May 24, 2023
dff1da6
added a read switch case to read in grid layer num
saaramahmoudi May 24, 2023
09811dd
updated rr_graph_uxsdcxx to read layer from grid_loc
saaramahmoudi May 24, 2023
430716f
Merge branch 'master' into place_3d
saaramahmoudi May 24, 2023
25f0370
updated grid_loc data structure for reading new formatted rr_graph
saaramahmoudi May 25, 2023
e3260ae
Merge branch 'place_3d' of https://github.com/verilog-to-routing/vtr-…
saaramahmoudi May 25, 2023
891c474
Merge branch 'master' into place_3d
saaramahmoudi May 25, 2023
29d3008
Merge branch 'master' into place_3d
saaramahmoudi May 26, 2023
46fc5e1
add comments on contraints_writer and RegionRectCoord
amin1377 May 29, 2023
5953bec
add comments on compressed grid layer - add assertion to ensure havin…
amin1377 May 29, 2023
1148e4c
Commenting out symbiflow tests from vtr nightly test 1
amin1377 May 29, 2023
72041db
make format
amin1377 May 29, 2023
24c328e
fix the arch dir in the config files of noc 3d tests
amin1377 May 30, 2023
cdc5e14
add layer_num dim to t_src_opin_delays & t_chan_ipins_delays
amin1377 May 31, 2023
70d62ce
prevent dijkstra flood to go to a different layer - add layer_num to …
amin1377 May 31, 2023
0e1bfb4
adapt router_lookahead_extended_map to the additional dimention of sr…
amin1377 May 31, 2023
6875e5f
make format
amin1377 May 31, 2023
e00c477
use from_layer to access src_opin_delays in get_expected_delay_and_co…
amin1377 May 31, 2023
758ca95
remove a redundant var - fix the seg fault - use from layer to get th…
amin1377 May 31, 2023
3cd9410
Merge branch 'master' into place_3d
saaramahmoudi May 31, 2023
3f16553
Merge branch 'master' into place_3d
saaramahmoudi Jun 6, 2023
5074847
remove t_search_range and replace it with t_bb
amin1377 Jun 21, 2023
c3fac7b
commit get_compressed_grid_bounded_search_range and get_compressed_gr…
amin1377 Jun 21, 2023
e05dd36
comment of place delay model - add check for adjacent nodes to not be…
amin1377 Jun 21, 2023
f773979
explain build_tile_rr_graph functionality - make format
amin1377 Jun 21, 2023
6bb7455
merge with master - solve merge conflicts related to removing route t…
amin1377 Jun 21, 2023
dcd911f
write layer_num when writing the route file - read the route file eve…
amin1377 Jun 22, 2023
042bd16
updata nightly test one k6_frac_N8_22nm.xml/fir_pipe_39.v min_chan_w…
amin1377 Jun 23, 2023
13e219b
Merge branch 'master' into place_3d
saaramahmoudi Jun 27, 2023
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24 changes: 15 additions & 9 deletions libs/libarchfpga/src/device_grid.h
Original file line number Diff line number Diff line change
Expand Up @@ -50,7 +50,7 @@ class DeviceGrid {
* @brief Return the number of instances of the specified tile type on the specified layer. If the layer_num is -1, return the total number of instances of the specified tile type on all layers.
* @note This function should be used if count_instances() is called in the constructor.
*/
size_t num_instances(t_physical_tile_type_ptr type, int layer_num = 0) const;
size_t num_instances(t_physical_tile_type_ptr type, int layer_num) const;

/**
* @brief Returns the block types which limits the device size (may be empty if
Expand All @@ -59,23 +59,23 @@ class DeviceGrid {
std::vector<t_logical_block_type_ptr> limiting_resources() const { return limiting_resources_; }

///@brief Return the t_physical_tile_type_ptr at the specified location
inline t_physical_tile_type_ptr get_physical_type(size_t x, size_t y, int layer_num = 0) const {
return grid_[layer_num][x][y].type;
inline t_physical_tile_type_ptr get_physical_type(const t_physical_tile_loc& tile_loc) const {
return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].type;
}

///@brief Return the width offset of the tile at the specified location. The root location of the tile is where width_offset and height_offset are 0.
inline int get_width_offset(size_t x, size_t y, int layer_num = 0) const {
return grid_[layer_num][x][y].width_offset;
inline int get_width_offset(const t_physical_tile_loc& tile_loc) const {
return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].width_offset;
}

///@brief Return the height offset of the tile at the specified location. The root location of the tile is where width_offset and height_offset are 0
inline int get_height_offset(size_t x, size_t y, int layer_num = 0) const {
return grid_[layer_num][x][y].height_offset;
inline int get_height_offset(const t_physical_tile_loc& tile_loc) const {
return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].height_offset;
}

///@brief Return the metadata of the tile at the specified location
inline const t_metadata_dict* get_metadata(size_t x, size_t y, int layer_num = 0) const {
return grid_[layer_num][x][y].meta;
inline const t_metadata_dict* get_metadata(const t_physical_tile_loc& tile_loc) const {
return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].meta;
}

///@brief Given t_grid_tile, return the x coordinate of the tile on the given layer - Used by serializer functions
Expand All @@ -94,6 +94,12 @@ class DeviceGrid {
return diff % grid_.dim_size(2);
}

///@brief Given t_grid_tile, return the layer number of the tile - Used by serializer functions
inline int get_grid_loc_layer(const t_grid_tile*& grid_loc) const {
int layer_num = std::floor(static_cast<int>(grid_loc - &grid_.get(0)) / (width() * height()));
return layer_num;
}

///@brief Return the nth t_grid_tile on the given layer of the flattened grid - Used by serializer functions
inline const t_grid_tile* get_grid_locs_grid_loc(int n) const {
return &grid_.get(n);
Expand Down
25 changes: 25 additions & 0 deletions libs/libarchfpga/src/physical_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -814,6 +814,31 @@ struct t_physical_pin {
}
};

/**
* @brief Describes The location of a physical tile
* @param layer_num The die number of the physical tile. If the FPGA only has one die, or the physical tile is located
* on the base die, layer_num is equal to zero. If it is one the die above base die, it is one, etc.
* @param x The x location of the physical tile on the given die
* @param y The y location of the physical tile on the given die
*/
struct t_physical_tile_loc {
int x = OPEN;
int y = OPEN;
int layer_num = OPEN;

t_physical_tile_loc() = default;

t_physical_tile_loc(int x_val, int y_val, int layer_num_val)
: x(x_val)
, y(y_val)
, layer_num(layer_num_val) {}

// Returns true if this type location layer_num/x/y is not equal to OPEN
operator bool() const {
return !(x == OPEN || y == OPEN || layer_num == OPEN);
}
};

/** Describes I/O and clock ports of a physical tile type
*
* It corresponds to <port/> tags in the FPGA architecture description
Expand Down
8 changes: 4 additions & 4 deletions libs/librrgraph/CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -48,14 +48,14 @@ add_custom_target(
COMMAND ${CMAKE_COMMAND} -E make_directory rr_graph_generate
COMMAND ${CMAKE_COMMAND} -E chdir rr_graph_generate git clone https://github.com/duck2/uxsdcxx
COMMAND python3 -mpip install --user -r rr_graph_generate/uxsdcxx/requirements.txt
COMMAND ${CMAKE_COMMAND} -E chdir rr_graph_generate python3 uxsdcxx/uxsdcxx.py ${CMAKE_CURRENT_SOURCE_DIR}/src/base/rr_graph.xsd
COMMAND ${CMAKE_COMMAND} -E chdir rr_graph_generate python3 uxsdcxx/uxsdcap.py ${CMAKE_CURRENT_SOURCE_DIR}/src/base/rr_graph.xsd
COMMAND ${CMAKE_COMMAND} -E chdir rr_graph_generate python3 uxsdcxx/uxsdcxx.py ${CMAKE_CURRENT_SOURCE_DIR}/src/io/rr_graph.xsd
COMMAND ${CMAKE_COMMAND} -E chdir rr_graph_generate python3 uxsdcxx/uxsdcap.py ${CMAKE_CURRENT_SOURCE_DIR}/src/io/rr_graph.xsd
COMMAND ${CMAKE_COMMAND} -E copy
rr_graph_generate/rr_graph_uxsdcxx.h
rr_graph_generate/rr_graph_uxsdcxx_capnp.h
rr_graph_generate/rr_graph_uxsdcxx_interface.h
${CMAKE_CURRENT_SOURCE_DIR}/src/base/gen
${CMAKE_CURRENT_SOURCE_DIR}/src/io/gen
COMMAND ${CMAKE_COMMAND} -E copy rr_graph_generate/rr_graph_uxsdcxx.capnp ${CMAKE_CURRENT_SOURCE_DIR}/../libvtrcapnproto/gen
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/src/base/rr_graph.xsd
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/src/io/rr_graph.xsd
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
)
22 changes: 17 additions & 5 deletions libs/librrgraph/src/base/check_rr_graph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -234,9 +234,11 @@ void check_rr_graph(const RRGraphView& rr_graph,
size_t inode = (size_t)rr_node;
t_rr_type rr_type = rr_graph.node_type(rr_node);
int ptc_num = rr_graph.node_ptc_num(rr_node);
int layer_num = rr_graph.node_layer(rr_node);
int xlow = rr_graph.node_xlow(rr_node);
int ylow = rr_graph.node_ylow(rr_node);
t_physical_tile_type_ptr type = grid.get_physical_type(xlow, ylow);

t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num});

if (rr_type == IPIN || rr_type == OPIN) {
// #TODO: No edges are added for internal pins. However, they need to be checked somehow!
Expand Down Expand Up @@ -273,7 +275,9 @@ void check_rr_graph(const RRGraphView& rr_graph,
if (!is_chain && !is_fringe && !is_wire) {
if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) {
if (has_adjacent_channel(rr_graph, grid, node)) {
auto block_type = grid.get_physical_type(rr_graph.node_xlow(rr_node), rr_graph.node_ylow(rr_node));
auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node),
rr_graph.node_ylow(rr_node),
rr_graph.node_layer(rr_node)});
std::string pin_name = block_type_pin_index_to_name(block_type, rr_graph.node_pin_num(rr_node), is_flat);
/* Print error messages for all the sides that a node may appear */
for (const e_side& node_side : SIDES) {
Expand Down Expand Up @@ -312,7 +316,9 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device
int ipin;
t_physical_tile_type_ptr type;

type = grid.get_physical_type(rr_graph.node_xlow(inode), rr_graph.node_ylow(inode));
type = grid.get_physical_type({rr_graph.node_xlow(inode),
rr_graph.node_ylow(inode),
rr_graph.node_layer(inode)});

if (rr_graph.node_type(inode) != IPIN)
return (false);
Expand All @@ -335,7 +341,7 @@ void check_rr_node(const RRGraphView& rr_graph,

//Make sure over-flow doesn't happen
VTR_ASSERT(inode >= 0);
int xlow, ylow, xhigh, yhigh, ptc_num, capacity;
int xlow, ylow, xhigh, yhigh, layer_num, ptc_num, capacity;
t_rr_type rr_type;
t_physical_tile_type_ptr type;
int nodes_per_chan, tracks_per_node;
Expand All @@ -348,6 +354,7 @@ void check_rr_node(const RRGraphView& rr_graph,
xhigh = rr_graph.node_xhigh(rr_node);
ylow = rr_graph.node_ylow(rr_node);
yhigh = rr_graph.node_yhigh(rr_node);
layer_num = rr_graph.node_layer(rr_node);
ptc_num = rr_graph.node_ptc_num(rr_node);
capacity = rr_graph.node_capacity(rr_node);
cost_index = rr_graph.node_cost_index(rr_node);
Expand All @@ -363,6 +370,11 @@ void check_rr_node(const RRGraphView& rr_graph,
"in check_rr_node: rr endpoints (%d,%d) and (%d,%d) are out of range.\n", xlow, ylow, xhigh, yhigh);
}

if (layer_num < 0 || layer_num > int(grid.get_num_layers()) - 1) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: rr endpoints layer_num (%d) is out of range.\n", layer_num);
}

if (ptc_num < 0) {
VPR_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num);
Expand All @@ -374,7 +386,7 @@ void check_rr_node(const RRGraphView& rr_graph,
}

/* Check that the segment is within the array and such. */
type = grid.get_physical_type(xlow, ylow);
type = grid.get_physical_type({xlow, ylow, layer_num});

switch (rr_type) {
case SOURCE:
Expand Down
7 changes: 4 additions & 3 deletions libs/librrgraph/src/base/rr_graph_builder.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -28,26 +28,27 @@ MetadataStorage<std::tuple<int, int, short>>& RRGraphBuilder::rr_edge_metadata()
void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
t_rr_type node_type = node_storage_.node_type(node);
short node_ptc_num = node_storage_.node_ptc_num(node);
short node_layer = node_storage_.node_layer(node);
for (int ix = node_storage_.node_xlow(node); ix <= node_storage_.node_xhigh(node); ix++) {
for (int iy = node_storage_.node_ylow(node); iy <= node_storage_.node_yhigh(node); iy++) {
switch (node_type) {
case SOURCE:
case SINK:
case CHANY:
node_lookup_.add_node(node, ix, iy, node_type, node_ptc_num, SIDES[0]);
node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, SIDES[0]);
break;
case CHANX:
/* Currently need to swap x and y for CHANX because of chan, seg convention
* TODO: Once the builders is reworked for use consistent (x, y) convention,
* the following swapping can be removed
*/
node_lookup_.add_node(node, iy, ix, node_type, node_ptc_num, SIDES[0]);
node_lookup_.add_node(node,node_layer, iy, ix, node_type, node_ptc_num, SIDES[0]);
break;
case OPIN:
case IPIN:
for (const e_side& side : SIDES) {
if (node_storage_.is_node_on_specific_side(node, side)) {
node_lookup_.add_node(node, ix, iy, node_type, node_ptc_num, side);
node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side);
}
}
break;
Expand Down
10 changes: 10 additions & 0 deletions libs/librrgraph/src/base/rr_graph_builder.h
Original file line number Diff line number Diff line change
Expand Up @@ -165,6 +165,11 @@ class RRGraphBuilder {
node_storage_.set_node_coordinates(id, x1, y1, x2, y2);
}

/** @brief Set the node layer (specifies which die the node is located at) */
inline void set_node_layer(RRNodeId id, short layer){
node_storage_.set_node_layer(id,layer);
}

/** @brief The ptc_num carries different meanings for different node types
* (true in VPR RRG that is currently supported, may not be true in customized RRG)
* CHANX or CHANY: the track id in routing channels
Expand All @@ -179,6 +184,11 @@ class RRGraphBuilder {
node_storage_.set_node_ptc_num(id, new_ptc_num);
}

/** @brief set the layer number at which RRNodeId is located at */
inline void set_node_layer(RRNodeId id, int layer){
node_storage_.set_node_layer(id, layer);
}

/** @brief set_node_pin_num() is designed for logic blocks, which are IPIN and OPIN nodes */
inline void set_node_pin_num(RRNodeId id, int new_pin_num) {
node_storage_.set_node_pin_num(id, new_pin_num);
Expand Down
6 changes: 6 additions & 0 deletions libs/librrgraph/src/base/rr_graph_storage.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -624,6 +624,10 @@ const char* t_rr_graph_storage::node_side_string(RRNodeId id) const {
return SIDE_STRING[NUM_SIDES];
}

void t_rr_graph_storage::set_node_layer(RRNodeId id, short layer) {
node_layer_[id] = layer;
}

void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) {
node_ptc_[id].ptc_.pin_num = new_ptc_num; //TODO: eventually remove
}
Expand Down Expand Up @@ -777,6 +781,7 @@ int t_rr_graph_view::node_class_num(RRNodeId id) const {
return get_node_class_num(node_storage_, node_ptc_, id);
}


t_rr_graph_view t_rr_graph_storage::view() const {
VTR_ASSERT(partitioned_);
VTR_ASSERT(node_storage_.size() == node_fan_in_.size());
Expand All @@ -785,6 +790,7 @@ t_rr_graph_view t_rr_graph_storage::view() const {
vtr::make_const_array_view_id(node_ptc_),
vtr::make_const_array_view_id(node_first_edge_),
vtr::make_const_array_view_id(node_fan_in_),
vtr::make_const_array_view_id(node_layer_),
vtr::make_const_array_view_id(edge_src_node_),
vtr::make_const_array_view_id(edge_dest_node_),
vtr::make_const_array_view_id(edge_switch_));
Expand Down
30 changes: 30 additions & 0 deletions libs/librrgraph/src/base/rr_graph_storage.h
Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@ struct alignas(16) t_rr_node_data {
} dir_side_;

uint16_t capacity_ = 0;

};

// t_rr_node_data is a key data structure, so fail at compile time if the
Expand Down Expand Up @@ -226,6 +227,14 @@ class t_rr_graph_storage {
return node_fan_in_[id];
}

/* Find the layer number that RRNodeId is located at.
* it is zero if the FPGA only has one die.
* The layer number start from the base die (base die: 0, the die above it: 1, etc.)
* */
short node_layer(RRNodeId id) const{
return node_layer_[id];
}

// This prefetechs hot RR node data required for optimization.
//
// Note: This is optional, but may lower time spent on memory stalls in
Expand Down Expand Up @@ -393,6 +402,7 @@ class t_rr_graph_storage {
make_room_in_vector(&node_storage_, size_t(elem_position));
node_ptc_.reserve(node_storage_.capacity());
node_ptc_.resize(node_storage_.size());
node_layer_.resize(node_storage_.size());
}

// Reserve storage for RR nodes.
Expand All @@ -401,6 +411,7 @@ class t_rr_graph_storage {
VTR_ASSERT(!edges_read_);
node_storage_.reserve(size);
node_ptc_.reserve(size);
node_layer_.reserve(size);
}

// Resize node storage to accomidate size RR nodes.
Expand All @@ -409,6 +420,7 @@ class t_rr_graph_storage {
VTR_ASSERT(!edges_read_);
node_storage_.resize(size);
node_ptc_.resize(size);
node_layer_.resize(size);
}

// Number of RR nodes that can be accessed.
Expand All @@ -429,6 +441,7 @@ class t_rr_graph_storage {
node_ptc_.clear();
node_first_edge_.clear();
node_fan_in_.clear();
node_layer_.clear();
seen_edge_.clear();
edge_src_node_.clear();
edge_dest_node_.clear();
Expand All @@ -448,6 +461,7 @@ class t_rr_graph_storage {
node_ptc_.shrink_to_fit();
node_first_edge_.shrink_to_fit();
node_fan_in_.shrink_to_fit();
node_layer_.shrink_to_fit();
seen_edge_.shrink_to_fit();
edge_src_node_.shrink_to_fit();
edge_dest_node_.shrink_to_fit();
Expand All @@ -461,6 +475,7 @@ class t_rr_graph_storage {
VTR_ASSERT(!edges_read_);
node_storage_.emplace_back();
node_ptc_.emplace_back();
node_layer_.emplace_back();
}

// Given `order`, a vector mapping each RRNodeId to a new one (old -> new),
Expand All @@ -479,6 +494,7 @@ class t_rr_graph_storage {

void set_node_type(RRNodeId id, t_rr_type new_type);
void set_node_coordinates(RRNodeId id, short x1, short y1, short x2, short y2);
void set_node_layer(RRNodeId id, short layer);
void set_node_cost_index(RRNodeId, RRIndexedDataId new_cost_index);
void set_node_rc_index(RRNodeId, NodeRCIndex new_rc_index);
void set_node_capacity(RRNodeId, short new_capacity);
Expand Down Expand Up @@ -670,6 +686,12 @@ class t_rr_graph_storage {
// Fan in counts for each RR node.
vtr::vector<RRNodeId, t_edge_size> node_fan_in_;

// Layer number that each RR node is located at
// Layer number refers to the die that the node belongs to. The layer number of base die is zero and die above it one, etc.
// This data is also considered as a hot data since it is used in inner loop of router, but since it didn't fit nicely into t_rr_node_data due to alignment issues, we had to store it
// in a separate vector.
vtr::vector<RRNodeId, short> node_layer_;

// Edge storage.
vtr::vector<RREdgeId, RRNodeId> edge_src_node_;
vtr::vector<RREdgeId, RRNodeId> edge_dest_node_;
Expand Down Expand Up @@ -721,13 +743,15 @@ class t_rr_graph_view {
const vtr::array_view_id<RRNodeId, const t_rr_node_ptc_data> node_ptc,
const vtr::array_view_id<RRNodeId, const RREdgeId> node_first_edge,
const vtr::array_view_id<RRNodeId, const t_edge_size> node_fan_in,
const vtr::array_view_id<RRNodeId, const short> node_layer,
const vtr::array_view_id<RREdgeId, const RRNodeId> edge_src_node,
const vtr::array_view_id<RREdgeId, const RRNodeId> edge_dest_node,
const vtr::array_view_id<RREdgeId, const short> edge_switch)
: node_storage_(node_storage)
, node_ptc_(node_ptc)
, node_first_edge_(node_first_edge)
, node_fan_in_(node_fan_in)
, node_layer_(node_layer)
, edge_src_node_(edge_src_node)
, edge_dest_node_(edge_dest_node)
, edge_switch_(edge_switch) {}
Expand Down Expand Up @@ -784,6 +808,11 @@ class t_rr_graph_view {
return node_fan_in_[id];
}

/* Retrieve layer(die) number that RRNodeId is located at */
short node_layer(RRNodeId id) const{
return node_layer_[id];
}

// This prefetechs hot RR node data required for optimization.
//
// Note: This is optional, but may lower time spent on memory stalls in
Expand Down Expand Up @@ -824,6 +853,7 @@ class t_rr_graph_view {
vtr::array_view_id<RRNodeId, const t_rr_node_ptc_data> node_ptc_;
vtr::array_view_id<RRNodeId, const RREdgeId> node_first_edge_;
vtr::array_view_id<RRNodeId, const t_edge_size> node_fan_in_;
vtr::array_view_id<RRNodeId, const short> node_layer_;
vtr::array_view_id<RREdgeId, const RRNodeId> edge_src_node_;
vtr::array_view_id<RREdgeId, const RRNodeId> edge_dest_node_;
vtr::array_view_id<RREdgeId, const short> edge_switch_;
Expand Down
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