Fix DSP blocks synthesis bug in Yosys+Odin-II

ODIN_II/SRC/BLIFElaborate.cpp

@@ -301,6 +301,7 @@ void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlis
         case PAD_NODE:     //fallthrough
         case INPUT_NODE:   //fallthrough
         case OUTPUT_NODE:  //fallthrough
+        case HARD_IP:      //fallthrough
         case BUF_NODE:     //fallthrough
         case BITWISE_NOT:  //fallthrough
         case BITWISE_AND:  //fallthrough
@@ -312,7 +313,6 @@ void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlis
             /* some are already resolved for this phase */
             break;
         }
-        case HARD_IP:
         case ADDER_FUNC:
         case CARRY_FUNC:
         case CLOCK_NODE:

ODIN_II/SRC/BLIFReader.cpp

@@ -349,31 +349,36 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
         char* subcircuit_stripped_name = get_stripped_name(subcircuit_name);
         /* check for coarse-grain configuration */
         if (configuration.coarsen) {
-            new_node->type = yosys_subckt_strmap[subcircuit_name];
+            if (yosys_subckt_strmap.find(subcircuit_name) != yosys_subckt_strmap.end())
+                new_node->type = yosys_subckt_strmap[subcircuit_name];
 
-            if (subcircuit_stripped_name && new_node->type == NO_OP)
+            if (new_node->type == NO_OP && yosys_subckt_strmap.find(subcircuit_stripped_name) != yosys_subckt_strmap.end())
                 new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
 
             if (new_node->type == NO_OP) {
                 char new_name[READ_BLIF_BUFFER];
                 vtr::free(new_node->name);
                 /* in case of weird names, need to add memories manually */
-                if (ports->count == 5) {
+                int sc_spot = -1;
+                char* yosys_subckt_str = NULL;
+                if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
                     /* specify node type */
-                    new_node->type = yosys_subckt_strmap[SINGLE_PORT_RAM_string];
+                    new_node->type = yosys_subckt_strmap[yosys_subckt_str];
                     /* specify node name */
-                    odin_sprintf(new_name, "\\%s~%ld", SINGLE_PORT_RAM_string, hard_block_number - 1);
-                    new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
-                } else if (ports->count == 9) {
+                    odin_sprintf(new_name, "\\%s~%ld", yosys_subckt_str, hard_block_number - 1);
+                } else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
                     /* specify node type */
-                    new_node->type = yosys_subckt_strmap[DUAL_PORT_RAM_string];
+                    new_node->type = HARD_IP;
                     /* specify node name */
-                    odin_sprintf(new_name, "\\%s~%ld", DUAL_PORT_RAM_string, hard_block_number - 1);
-                    new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
+                    odin_sprintf(new_name, "\\%s~%ld", subcircuit_stripped_name, hard_block_number - 1);
                 } else {
                     error_message(PARSE_BLIF, unknown_location,
-                                  "Unsupported sub-circuit type (%s) in BLIF file.\n", subcircuit_name);
+                                  "Unsupported subcircuit type (%s) in BLIF file.\n", subcircuit_name);
                 }
+                new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
+
+                // CLEAN UP
+                vtr::free(yosys_subckt_str);
             }
 
             if (new_node->type == BRAM) {
@@ -410,7 +415,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
 
     if (!model)
         error_message(PARSE_BLIF, unknown_location,
-                      "Failed to retrieve sub-circuit model (%s)\n", subcircuit_name);
+                      "Failed to retrieve subcircuit model (%s)\n", subcircuit_name);
 
     /* Add input and output ports to the new node. */
     else {
@@ -481,7 +486,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
         }
 
         // Create a fake ast node.
-        if (!configuration.coarsen) {
+        if (!configuration.coarsen || new_node->type == HARD_IP) {
             new_node->related_ast_node = create_node_w_type(HARD_BLOCK, my_location);
             new_node->related_ast_node->children = (ast_node_t**)vtr::calloc(1, sizeof(ast_node_t*));
             new_node->related_ast_node->identifier_node = create_tree_node_id(vtr::strdup(subcircuit_name), my_location);
@@ -2147,8 +2152,11 @@ void BLIF::Reader::hard_block_sensitivities(const char* subckt_name, nnode_t* ne
     char* ptr;
     char* buffer = NULL;
     attr_t* attributes = new_node->attributes;
+    operation_list op = (yosys_subckt_strmap.find(subckt_name) != yosys_subckt_strmap.end())
+                            ? yosys_subckt_strmap[subckt_name]
+                            : NO_OP;
 
-    if (need_params(yosys_subckt_strmap[subckt_name])) {
+    if (need_params(op)) {
         while (getbline(buffer, READ_BLIF_BUFFER, file)) {
             my_location.line += 1;
             ptr = vtr::strtok(buffer, TOKENS, file, buffer);

ODIN_II/SRC/BLIFWriter.cpp

@@ -74,8 +74,15 @@ inline void BLIF::Writer::_write(const netlist_t* netlist) {
     output_blif(this->output_file, netlist);
 }
 
-inline void BLIF::Writer::_create_file(const file_type_e /* file_type */) {
-    this->output_file = create_blif(global_args.output_file.value().c_str());
+inline void BLIF::Writer::_create_file(const char* file_name, const file_type_e file_type) {
+    // validate the file_name pionter
+    oassert(file_name);
+    // validate the file type
+    if (file_type != _BLIF)
+        error_message(UTIL, unknown_location,
+                      "BLIF back-end entity cannot create file types(%d) other than BLIF", file_type);
+    // create the BLIF file and set it as the output file
+    this->output_file = create_blif(file_name);
 }
 /**
  * ---------------------------------------------------------------------------------------------

ODIN_II/SRC/GenericIO.cpp

@@ -44,7 +44,7 @@ void GenericIO::_write(const netlist_t* /* netlist */) {
                   "Function \"%s\" is called for reading the input file without definition provided!\n", __PRETTY_FUNCTION__);
 }
 
-void GenericIO::_create_file(const file_type_e /* file_type */) {
+void GenericIO::_create_file(const char* /* file_name */, const file_type_e /* file_type */) {
     error_message(UTIL, unknown_location,
                   "Function \"%s\" is called for reading the input file without definition provided!\n", __PRETTY_FUNCTION__);
 }

ODIN_II/SRC/GenericWriter.cpp

@@ -37,13 +37,16 @@ GenericWriter::GenericWriter()
     : GenericIO() {
     this->output_file = NULL;
     this->blif_writer = NULL;
+    this->verilog_writer = NULL;
 }
 
 GenericWriter::~GenericWriter() {
     if (this->output_file)
         fclose(this->output_file);
     if (this->blif_writer)
         delete this->blif_writer;
+    if (this->verilog_writer)
+        delete this->verilog_writer;
 }
 
 inline void GenericWriter::_write(const netlist_t* netlist) {
@@ -52,12 +55,12 @@ inline void GenericWriter::_write(const netlist_t* netlist) {
             this->write_blif(netlist);
             break;
         }
+        case (file_type_e::_VERILOG): {
+            this->write_verilog(netlist);
+            break;
+        }
         /**
          * [TODO]
-         *  case (file_type_e::_VERILOG): {
-         * netlist = this->write_verilog();
-         * break;
-         * }
          *  case (file_type_e::_EBLIF): {
          * netlist = this->write_verilog();
          * break;
@@ -79,22 +82,30 @@ inline void GenericWriter::write_blif(const netlist_t* netlist) {
     this->blif_writer->_write(netlist);
 }
 
-inline void GenericWriter::_create_file(const file_type_e file_type) {
+inline void GenericWriter::write_verilog(const netlist_t* netlist) {
+    oassert(this->verilog_writer);
+    this->verilog_writer->_write(netlist);
+}
+
+inline void GenericWriter::_create_file(const char* file_name, const file_type_e file_type) {
+    // validate the file_name pointer
+    oassert(file_name);
+
     switch (file_type) {
         case (file_type_e::_BLIF): {
             if (!this->blif_writer) {
                 this->blif_writer = new BLIF::Writer();
-                this->blif_writer->_create_file(file_type);
+                this->blif_writer->_create_file(file_name, file_type);
             }
             break;
         }
+        case (file_type_e::_VERILOG): {
+            this->verilog_writer = new Verilog::Writer();
+            this->verilog_writer->_create_file(file_name, file_type);
+            break;
+        }
         /**
          * [TODO]
-         *  case (file_type_e::_VERILOG): {
-         * this->verilog_writer = new VERILOG::Writer();
-         * this->verilog_writer->_create_file();
-         * break;
-         * }
          *  case (file_type_e::_EBLIF): {
          * this->eblif_writer = new EBLIF::Writer();
          * this->eblif_writer->_create_file();