Fix DSP blocks synthesis bug in Yosys+Odin-II#1953

Merged

sdamghan merged 7 commits intoverilog-to-routing:masterfrom

sdamghan:fix_yosys_odin_dsp

Jan 29, 2022

Commits on Jan 28, 2022

[Yosys+Odin]: Add a Verilog entity to generate DSPs' declaration as blackboxes
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[Yosys+Odin]: Add "hierarchy -purge_lib" to the yosys script to remove unused bb definitions
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[Yosys+Odin]: - pass user-defined DSPs untouched to the partial mapping phase
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[Yosys+Odin]: formatting the new code
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[Arch]: remove additional definition of "reset" port for the fp16_sop2_accum DSP slice
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[Yosys+Odin]: Update the Yosys+Odin/Koios task golden results
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[Yosys+Odin]: remove hardcodded DPRAM/SPRAM detection in BLIF Reader
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