Yosys+VTR

.github/kokoro/continuous/yosys_test.cfg

@@ -1,6 +1,6 @@
 # Format: //devtools/kokoro/config/proto/build.proto
-# vtr_reg_yosys_odin test runs the VTR benchmarks through 
-# the entire VTR with Yosys+Odin-II as the first CAD tool 
+# vtr_reg_yosys test runs the VTR benchmarks through 
+# the entire VTR with Yosys as the first CAD tool 
 
 build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
 
@@ -48,12 +48,12 @@ env_vars {
 #Use default build configuration
 env_vars {
   key: "VTR_CMAKE_PARAMS"
-  value: ""
+  value: "-DWITH_YOSYS=ON"
 }
 
 env_vars {
   key: "VTR_TEST"
-  value: "odin_reg_strong"
+  value: "vtr_reg_yosys"
 }
 
 #Options for run_reg_test.py
@@ -65,5 +65,5 @@ env_vars {
 
 env_vars {
   key: "NUM_CORES"
-  value: "3"
-}
+  value: "8"
+}

.github/kokoro/presubmit/yosys_test.cfg

@@ -1,6 +1,6 @@
 # Format: //devtools/kokoro/config/proto/build.proto
-# vtr_reg_yosys_odin test runs the VTR benchmarks through 
-# the entire VTR with Yosys+Odin-II as the first CAD tool
+# vtr_reg_yosys test runs the VTR benchmarks through 
+# the entire VTR with Yosys as the first CAD tool
 
 build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
 
@@ -48,12 +48,12 @@ env_vars {
 #Use default build configuration
 env_vars {
   key: "VTR_CMAKE_PARAMS"
-  value: ""
+  value: "-DWITH_YOSYS=ON"
 }
 
 env_vars {
   key: "VTR_TEST"
-  value: "odin_reg_strong"
+  value: "vtr_reg_yosys"
 }
 
 #Options for run_reg_test.py

CMakeLists.txt

@@ -52,6 +52,7 @@ option(ODIN_TIDY "Enable building odin with clang tidy" OFF)
 option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
+option(WITH_YOSYS "Enable building Yosys" OFF)
 option(ODIN_USE_YOSYS "Enable building Yosys" OFF)
 
 set(VTR_VERSION_MAJOR 8)
@@ -381,7 +382,10 @@ if(${WITH_ABC})
     add_subdirectory(ace2)
 endif()
 add_subdirectory(utils)
-if(${WITH_ODIN})
+# define cmake params to compile Yosys
+if(${WITH_YOSYS})
+    add_definitions("-D_YOSYS_")
+elseif(${WITH_ODIN})
     add_subdirectory(ODIN_II)
     # blifexplorer depends on odin
     if(${WITH_BLIFEXPLORER})

ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json

@@ -58,15 +58,15 @@
         "Latch Drivers": 1,
         "Pi": 273,
         "Po": 193,
-        "logic element": 4141,
-        "latch": 857,
-        "Adder": 136,
+        "logic element": 4204,
+        "latch": 871,
+        "Adder": 151,
         "Memory": 32,
         "generic logic size": 4,
         "Longest Path": 428,
         "Average Path": 4,
-        "Estimated LUTs": 4435,
-        "Total Node": 5167
+        "Estimated LUTs": 4510,
+        "Total Node": 5259
     },
     "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm": {
         "test_name": "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm",

ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json

@@ -101,15 +101,15 @@
         "Latch Drivers": 1,
         "Pi": 273,
         "Po": 193,
-        "logic element": 4141,
-        "latch": 857,
-        "Adder": 136,
+        "logic element": 4204,
+        "latch": 871,
+        "Adder": 151,
         "Memory": 32,
         "generic logic size": 4,
         "Longest Path": 428,
         "Average Path": 4,
-        "Estimated LUTs": 4435,
-        "Total Node": 5167
+        "Estimated LUTs": 4510,
+        "Total Node": 5259
     },
     "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm": {
         "test_name": "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm",

ODIN_II/regression_test/benchmark/verilog/full/mcml.v

@@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;	
@@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 36'b000000000000000000000000000000000000;
-assign dont_care_out = 36'b000000000000000000000000000000000000;
+// assign dont_care_out = 36'b000000000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 36;
@@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 18'b000000000000000000;
-assign dont_care_out = 18'b000000000000000000;
+// assign dont_care_out = 18'b000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 18;
@@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 8'b00000000;
-assign dont_care_out = 8'b00000000;
+// assign dont_care_out = 8'b00000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 8;

ODIN_II/regression_test/benchmark/verilog/large/boundtop.v

@@ -222,7 +222,7 @@ wire[63:0] tldata;
         resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); 
         rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); 
         boundcontroller  boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01);
-        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01);
+        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10);
         resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); 
 
 assign raygroupout = raygroupout01 | raygroupout10 ;
@@ -287,7 +287,7 @@ assign raygroupout = raygroupout01 | raygroupout10 ;
 
     resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0); 
 
-    // global reset as an output is undriven!
+    // global reset as an output should be driven!
     assign globalreset = pglobalreset;
 
  endmodule
@@ -2821,4 +2821,4 @@ endmodule
           end 
        end 
     end 
- endmodule
+ endmodule

libs/EXTERNAL/CMakeLists.txt

@@ -14,9 +14,9 @@ if(VPR_USE_EZGL STREQUAL "on")
     add_subdirectory(libezgl)
 endif()
 
-# The VTR root CMakeFile initializes the ODIN_USE_YOSYS
+# The VTR root CMakeFile initializes the ODIN_USE_YOSYS or WITH_YOSYS
 # Yosys is compiled only if the user ask for it
-if(${ODIN_USE_YOSYS})
+if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
     add_subdirectory(libyosys)
 endif()
 

libs/EXTERNAL/libyosys/CMakeLists.txt

@@ -1,42 +1,41 @@
 cmake_minimum_required(VERSION 3.9)
 
-# [KNOWN_ISSUE]: if ODIN_USE_YOSYS is active, abc will be compiled 
-# for the second time inside Yosys, since Yosys uses a different
-# version of abc
 project("libyosys")
 
 # Create a target out of the library compilation result
 SET(LIB_FILE ${CMAKE_CURRENT_SOURCE_DIR}/libyosys.so)
 SET(BINARY_LIB_FILE ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/libyosys.so)
+SET(YOSYS_EXEC ${CMAKE_CURRENT_SOURCE_DIR}/yosys)
+SET(BINARY_EXEC_FILE ${CMAKE_CURRENT_BINARY_DIR}/bin/yosys)
 SET(YOSYS_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR})
 
 # handle make program with both ninja and unix style
 set(MAKE_PROGRAM "$(MAKE)")
 # handle cppflags to suppress yosys warning with both ninja and unix style
 set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w")
 if(${CMAKE_GENERATOR} STREQUAL "Ninja")
-    set(MAKE_PROGRAM "make")
-    set(CURRENT_CPPFLAGS "-w")
+set(MAKE_PROGRAM "make")
+set(CURRENT_CPPFLAGS "-w")
 endif()
 
 # how to build the result of the library
-add_custom_command(OUTPUT  ${LIB_FILE} ${BINARY_LIB_FILE}
-                   COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" 
-                                           CPPFLAGS=${CURRENT_CPPFLAGS}
-                                           -j${CMAKE_BUILD_PARALLEL_LEVEL}
-                                           PREFIX=${CMAKE_CURRENT_BINARY_DIR}
-                                           > /dev/null
-                   COMMAND ${MAKE_PROGRAM} install 
-                                           PREFIX=${CMAKE_CURRENT_BINARY_DIR}
-                                           > /dev/null
-                   COMMAND ${CMAKE_COMMAND} -E 
-                                           make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
-                   COMMAND ${CMAKE_COMMAND} -E 
-                                           copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
-                   WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
+add_custom_command(OUTPUT  ${LIB_FILE} ${BINARY_LIB_FILE} ${YOSYS_EXEC} ${BINARY_EXEC_FILE}
+                COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" "ENABLE_ABC=0"
+                                        CPPFLAGS=${CURRENT_CPPFLAGS}
+                                        -j${CMAKE_BUILD_PARALLEL_LEVEL}
+                                        PREFIX=${CMAKE_CURRENT_BINARY_DIR}
+                                        > /dev/null
+                COMMAND ${MAKE_PROGRAM} install 
+                                        PREFIX=${CMAKE_CURRENT_BINARY_DIR}
+                                        > /dev/null
+                COMMAND ${CMAKE_COMMAND} -E 
+                                        make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
+                COMMAND ${CMAKE_COMMAND} -E 
+                                        copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
+                WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
 
 # create a target out of the library compilation result
-add_custom_target(yosys DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE})
+add_custom_target(yosys ALL DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE})
 
 # create an library target out of the library compilation result
 add_library(libyosys SHARED IMPORTED GLOBAL)
@@ -47,3 +46,6 @@ set_target_properties(libyosys
     PROPERTIES PREFIX "" #Avoid extra 'lib' prefix
     IMPORTED_LOCATION ${LIB_FILE}
     INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS})
+
+
+install(FILES ${YOSYS_EXEC} DESTINATION ${CMAKE_CURRENT_BINARY_DIR})

vtr_flow/benchmarks/verilog/arm_core.v

@@ -4048,7 +4048,7 @@ reg  [31:0] r11 = 32'hdeadbeef;
 reg  [31:0] r12 = 32'hdeadbeef;
 reg  [31:0] r13 = 32'hdeadbeef;
 reg  [31:0] r14 = 32'hdeadbeef;
-reg  [23:0] r15 = 24'hc0ffee;
+reg  [23:0] r15; // see line: 4272
 
 wire  [31:0] r0_out;
 wire  [31:0] r1_out;
@@ -4268,7 +4268,8 @@ assign r15_out_rm_nxt = { i_status_bits_flags,
                           i_status_bits_firq_mask, 
                           i_pc, 
                           i_mode_exec};
-
+
+// if r15 is initialized => Yosys+ABC:A CI/CO pair share the name (u_execute.u_register_bank.r15[1]) but do not link directly
 assign r15_out_rn     = {6'd0, r15, 2'd0};
 
 

vtr_flow/benchmarks/verilog/boundtop.v

@@ -222,7 +222,7 @@ wire[63:0] tldata;
         resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); 
         rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); 
         boundcontroller  boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01);
-        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01);
+        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10);
         resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); 
 
 assign raygroupout = raygroupout01 | raygroupout10 ;

vtr_flow/benchmarks/verilog/mcml.v

@@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;	
@@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 36'b000000000000000000000000000000000000;
-assign dont_care_out = 36'b000000000000000000000000000000000000;
+// assign dont_care_out = 36'b000000000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 36;
@@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 18'b000000000000000000;
-assign dont_care_out = 18'b000000000000000000;
+// assign dont_care_out = 18'b000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 18;
@@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 8'b00000000;
-assign dont_care_out = 8'b00000000;
+// assign dont_care_out = 8'b00000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 8;