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Yosys+VTR#1844

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sdamghan merged 13 commits intoverilog-to-routing:masterverilog-to-routing/vtr-verilog-to-routing:masterfrom

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Oct 17, 2021

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Commits on Oct 16, 2021

• [Infra]: - add Yosys synthesizer to the VTR flow

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• [Infra]: - remove constant output drivers in mcml

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• [Infra]: - add blockbox attribute to SPRAM/DPRAM

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• [Infra]: fix yosys and run_vtr_flow lint errors

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• [Infra]: retrieve arm_core regs initialization value

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• [Infra]: - fix \$mem missed RD_EN port in yosys models

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• [Infra]: - fix SPRAM/DPRAM VPR packing issue for circuits synthesized by Yosys

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• [Odin]: - update boundtop in Odin-II regression tests

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• [Yosyslib]: - set extra memory address unconn instead of gnd, so VPR pack memory slices

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• [Infra]: add yosys regex files to parse yosys criteria in the final parse_results.txt

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• [Infra]: add vtr_reg_yosys golden resutls

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• [Infra]: adding VtR Yosys CI test

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• [Yosyslib]: add README to the yosyslib directory

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