Reorganizing vtr_flow/tasks

.github/kokoro/presubmit/nightly.cfg → .github/kokoro/presubmit/nightly_test1.cfg

@@ -51,7 +51,7 @@ env_vars {
 
 env_vars {
   key: "VTR_TEST"
-  value: "vtr_reg_nightly"
+  value: "vtr_reg_nightly_test1"
 }
 
 #Options for run_reg_test.py
@@ -63,5 +63,5 @@ env_vars {
 
 env_vars {
   key: "NUM_CORES"
-  value: "3"
+  value: "8"
 }

.github/kokoro/presubmit/nightly_test2.cfg

@@ -0,0 +1,67 @@
+# Format: //devtools/kokoro/config/proto/build.proto
+
+build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
+
+# 72 hours
+timeout_mins: 4320
+
+action {
+  define_artifacts {
+    # File types
+    regex: "**/*.out"
+    regex: "**/vpr_stdout.log"
+    regex: "**/parse_results.txt"
+    regex: "**/qor_results.txt"
+    regex: "**/pack.log"
+    regex: "**/place.log"
+    regex: "**/route.log"
+    regex: "**/*_qor.csv"
+    regex: "**/*.out.gz"
+    regex: "**/vpr_stdout.log.gz"
+    regex: "**/parse_results.txt.gz"
+    regex: "**/qor_results.txt.gz"
+    regex: "**/pack.log.gz"
+    regex: "**/place.log.gz"
+    regex: "**/route.log.gz"
+    regex: "**/*_qor.csv.gz"
+    strip_prefix: "github/vtr-verilog-to-routing/"
+  }
+}
+
+env_vars {
+  key: "KOKORO_TYPE"
+  value: "presubmit"
+}
+
+env_vars {
+  key: "KOKORO_DIR"
+  value: "vtr-verilog-to-routing"
+}
+
+env_vars {
+  key: "VTR_DIR"
+  value: "vtr-verilog-to-routing"
+}
+
+#Use default build configuration
+env_vars {
+  key: "VTR_CMAKE_PARAMS"
+  value: ""
+}
+
+env_vars {
+  key: "VTR_TEST"
+  value: "vtr_reg_nightly_test2"
+}
+
+#Options for run_reg_test.py
+# -show_failures: show tool failures in main log output
+env_vars {
+  key: "VTR_TEST_OPTIONS"
+  value: "-show_failures"
+}
+
+env_vars {
+  key: "NUM_CORES"
+  value: "8"
+}

.github/kokoro/presubmit/nightly_test3.cfg

@@ -0,0 +1,67 @@
+# Format: //devtools/kokoro/config/proto/build.proto
+
+build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
+
+# 72 hours
+timeout_mins: 4320
+
+action {
+  define_artifacts {
+    # File types
+    regex: "**/*.out"
+    regex: "**/vpr_stdout.log"
+    regex: "**/parse_results.txt"
+    regex: "**/qor_results.txt"
+    regex: "**/pack.log"
+    regex: "**/place.log"
+    regex: "**/route.log"
+    regex: "**/*_qor.csv"
+    regex: "**/*.out.gz"
+    regex: "**/vpr_stdout.log.gz"
+    regex: "**/parse_results.txt.gz"
+    regex: "**/qor_results.txt.gz"
+    regex: "**/pack.log.gz"
+    regex: "**/place.log.gz"
+    regex: "**/route.log.gz"
+    regex: "**/*_qor.csv.gz"
+    strip_prefix: "github/vtr-verilog-to-routing/"
+  }
+}
+
+env_vars {
+  key: "KOKORO_TYPE"
+  value: "presubmit"
+}
+
+env_vars {
+  key: "KOKORO_DIR"
+  value: "vtr-verilog-to-routing"
+}
+
+env_vars {
+  key: "VTR_DIR"
+  value: "vtr-verilog-to-routing"
+}
+
+#Use default build configuration
+env_vars {
+  key: "VTR_CMAKE_PARAMS"
+  value: ""
+}
+
+env_vars {
+  key: "VTR_TEST"
+  value: "vtr_reg_nightly_test3"
+}
+
+#Options for run_reg_test.py
+# -show_failures: show tool failures in main log output
+env_vars {
+  key: "VTR_TEST_OPTIONS"
+  value: "-show_failures"
+}
+
+env_vars {
+  key: "NUM_CORES"
+  value: "8"
+}

.github/kokoro/steps/vtr-test.sh

@@ -69,7 +69,10 @@ find vtr_flow/benchmarks/titan_blif/ -type f -not -name 'README.*' -delete
 find . -type f -regex ".*\.tar\.\(gz\|xz\)" -delete
 
 #Gzip output files from vtr_reg_nightly tests to lower working directory disk space
-find vtr_flow/tasks/regression_tests/vtr_reg_nightly/ -type f -print0 | xargs -0 -P $(nproc) gzip
+find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/ -type f -print0 | xargs -0 -P $(nproc) gzip
+find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/ -type f -print0 | xargs -0 -P $(nproc) gzip
+find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/ -type f -print0 | xargs -0 -P $(nproc) gzip
+
 
 # Make sure working directory doesn't exceed disk space limit!
 echo "Working directory size: $(du -sh)"

README.developers.md

@@ -754,12 +754,12 @@ There may be times when a regression test fails its QoR test because its golden_
 2. Next, generate new golden reference results using `parse_vtr_task.py` and the `-create_golden` option.
 
     ```shell
-    $ ../scripts/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -create_golden
+    $ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -create_golden
     ```
 3. Lastly, check that the results match with the `-check_golden` option
 
     ```shell
-    $ ../scripts/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -check_golden
+    $ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -check_golden
     ```
 Once the `-check_golden` command passes, the changes to the golden result can be committed so that the reg test will pass in future runs of vtr_reg_nightly.
 

vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml

@@ -132,7 +132,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -144,7 +144,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml

@@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml

@@ -159,7 +159,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -171,7 +171,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml

@@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml

@@ -158,7 +158,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -170,7 +170,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml

@@ -117,7 +117,8 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
         </fc>
         <pinlocations pattern="custom">
           <loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
-          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
+          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
+	  <loc side="top">clb.cin</loc>
         </pinlocations>
       </sub_tile>
     </tile>
@@ -153,7 +154,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -165,7 +166,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml

@@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
         </fc>
         <pinlocations pattern="custom">
           <loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
-          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
+          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
+	  <loc side="top">clb.cin</loc>
         </pinlocations>
       </sub_tile>
     </tile>
@@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml

@@ -132,7 +132,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -144,7 +144,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml

@@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
         </fc>
         <pinlocations pattern="custom">
           <loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
-          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
+          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
+	  <loc side="top">clb.cin</loc>
         </pinlocations>
       </sub_tile>
     </tile>
@@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml

@@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
         </fc>
         <pinlocations pattern="custom">
           <loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
-          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
+          <loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
+	  <loc side="top">clb.cin</loc>
         </pinlocations>
       </sub_tile>
     </tile>
@@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout>
-    <device_layout name="unnamed_device" width="17" height="17">
+    <fixed_layout name="unnamed_device" width="17" height="17">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
@@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
       <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </device_layout>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>