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ODIN: Introduce mixing of soft and hard logic as part of complex synthesis #1496

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Merged
merged 5 commits into from
Aug 21, 2020

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georgkrylov
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@georgkrylov georgkrylov commented Aug 21, 2020

Description

These changes address problem of ODIN's inability to use smaller number of multipliers than it is requested by the circuit. The changes are designed to work with multipliers first, should be easy to extend to adders and other blocks due to the class hierarchy introduced.

Motivation and Context

This change is required since sometimes, the synthesis flow for fixed layout would break even if the logic could be attempted to be implemented in soft logic that is not used otherwise. Moreover, setting a limit to number of hard blocks for auto layouts might change the shape of a device and could prevent from growing the device unnecessary.

The discussion about the design choices was happening in CAS-Atlantic fork of the repository, available by CAS-Atlantic#7

How Has This Been Tested?

The testing suite is included. Involves simulator verification for correctness, sanitizer checks for several cases: no arch, just mults, fracturable mults

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

This commit introduces a new optimization allowing to mix hard and soft
logic implementation for some circuits. This optimization allows
exploring frequency and device size trade-off. The optimization can be
enabled from command line options. The optimization currently works only
for architecture files that do not have hard adders. This commit also
changes the nnode_t structure shape

Signed-off-by: Georgiy Krylov <[email protected]>
This commit enables mixing hard and soft logic implementation as part of
the flow by defining a global reference to the mixing optimization con-
troller and doing changes to partial mapping stage to defer mapping of
hard multipliers. The commit also introduces command line arguments and
their default values, enabling to use the optimization.

Signed-off-by: Georgiy Krylov <[email protected]>
This commit introduces a new regression test based off of micro bench-
mark. The test implements half of the available multipliers in soft
logic for micro benchmark. It is a first test in the series, proposed as
a simple sanity check.

Signed-off-by: Georgiy Krylov <[email protected]>
This commit introduces a set of results for implementing half of the
available multiply operations in hard blocks, while the other half being
implemented in soft logic

Signed-off-by: Georgiy Krylov <[email protected]>
@probot-autolabeler probot-autolabeler bot added docs Documentation lang-cpp C/C++ code Odin Odin II Logic Synthesis Tool: Unsorted item tests labels Aug 21, 2020
@georgkrylov
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Hello @jeanlego, can you please review the proposed new feature for the public repository contribution?

@georgkrylov georgkrylov changed the title Complex synthesis ODIN: Introduce mixing of soft and hard logic as part of complex synthesis Aug 21, 2020
The problem was vtr_flow/scripts/python_libs/vtr/util.py:469:8: W0707: Consider explicitly re-raising using the 'from' keyword (raise-missing-from)

Signed-off-by: Georgiy Krylov <[email protected]>
@probot-autolabeler probot-autolabeler bot added infra Project Infrastructure lang-python Python code scripts Utility & Infrastructure scripts VTR Flow VTR Design Flow (scripts/benchmarks/architectures) labels Aug 21, 2020
@jeanlego
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jeanlego commented Aug 21, 2020

Can you link to the CAS Atlantic PR in The description too for posterity
Otherwise Looks good to me :)

Thanks for this

@georgkrylov georgkrylov reopened this Aug 21, 2020
@jeanlego jeanlego merged commit 688e51e into verilog-to-routing:master Aug 21, 2020
georgkrylov added a commit to georgkrylov/local-vtr-verilog-to-routing that referenced this pull request Oct 5, 2020
The commit addresses several errors
CID 212805:  API usage errors  (PRINTF_ARGS)
Related to verilog-to-routing#1496

Signed-off-by: Georgiy Krylov <[email protected]>
jeanlego pushed a commit that referenced this pull request Oct 6, 2020
The commit addresses several errors
CID 212805:  API usage errors  (PRINTF_ARGS)
Related to #1496

Signed-off-by: Georgiy Krylov <[email protected]>
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2 participants