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RR graph fix up #1448

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Sep 16, 2020
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235a61e
critical bug fix on rr_graph generation. Now input pins (receivers) h…
tangxifan Jul 8, 2020
bf03503
add comments to clarify the rr_graph builder for unique rr_nodes
tangxifan Jul 8, 2020
cf114c1
rephrase rr_graph comments and add check flags to ensure necessary no…
tangxifan Jul 10, 2020
e70832f
code format fix in rr_graph source files
tangxifan Jul 10, 2020
58587d2
code format fix
tangxifan Jul 10, 2020
226bf7e
show rr_node fan_in and fan_out in GUI message channel
tangxifan Jul 10, 2020
e800f3f
bug fix due to rebase
tangxifan Jul 22, 2020
f69b0bc
code clean-up for sanity and format checking
tangxifan Jul 23, 2020
82d034e
relax checking codes in rr_graph checker for IPINs/OPINs locating on …
tangxifan Jul 27, 2020
1d0c3f8
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
tangxifan Jul 30, 2020
50030b4
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
tangxifan Aug 3, 2020
985e65a
[Titan architecture] Apply full pin equivalence to LAB `data_out` port
tangxifan Aug 25, 2020
ee757db
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
tangxifan Sep 1, 2020
7810b59
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
tangxifan Sep 13, 2020
534e35f
[architecture file] improve routability for k6_N10_mem32K_40nm_i_or_o…
tangxifan Sep 13, 2020
e73d896
[Golden Result] update golden results to synchronize with QoR shift d…
tangxifan Sep 14, 2020
2b49f17
[VPR] remove comparison to boolean in rr_graph
tangxifan Sep 14, 2020
fd3ed26
[Golden Result] patch golden results for the analytic placer where th…
tangxifan Sep 14, 2020
14a154c
[Golden Results] Patch the vtr_nightly golden results due to the QoR …
tangxifan Sep 14, 2020
642f735
[Architecture File] Add important notes for k6_N10_mem32K_40nm_i_or_o…
tangxifan Sep 14, 2020
eaea31b
[Architecture File] Add comments for titan architecture to clarify th…
tangxifan Sep 15, 2020
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28 changes: 20 additions & 8 deletions vpr/src/route/check_rr_graph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -123,17 +123,23 @@ void check_rr_graph(const t_graph_type graph_type,

t_rr_type to_rr_type = device_ctx.rr_nodes[to_node].type();

//Only expect chan <-> chan connections to have multiple edges
if ((to_rr_type != CHANX && to_rr_type != CHANY)
|| (rr_type != CHANX && rr_type != CHANY)) {
/* Only expect the following cases to have multiple edges
* - chan <-> chan connections
* - IPIN <-> chan connections (unique rr_node for IPIN nodes on multiple sides)
* - OPIN <-> chan connections (unique rr_node for OPIN nodes on multiple sides)
*/
if (((to_rr_type != CHANX && to_rr_type != CHANY && rr_type != IPIN)
|| (rr_type != CHANX && rr_type != CHANY))
&& ((to_rr_type != CHANX && to_rr_type != CHANY)
|| (rr_type != CHANX && rr_type != CHANY && rr_type != OPIN))) {
VPR_ERROR(VPR_ERROR_ROUTE,
"in check_rr_graph: node %d (%s) connects to node %d (%s) %zu times - multi-connections only expected for CHAN->CHAN.\n",
inode, rr_node_typename[rr_type], to_node, rr_node_typename[to_rr_type], num_edges_to_node);
}

//Between two wire segments
VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY, "Expect channel type");
VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY, "Expect channel type");
VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == IPIN, "Expect channel type or input pin type");
VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type");

//While multiple connections between the same wires can be electrically legal,
//they are redundant if they are of the same switch type.
Expand All @@ -151,10 +157,16 @@ void check_rr_graph(const t_graph_type graph_type,
for (auto kv : switch_counts) {
if (kv.second <= 1) continue;

auto switch_type = device_ctx.rr_switch_inf[kv.first].type();
/* Redundant edges are not allowed for chan <-> chan connections
* but allowed for input pin <-> chan or output pin <-> chan connections
*/
if ((to_rr_type == CHANX || to_rr_type == CHANY)
&& (rr_type == CHANX || rr_type == CHANY)) {
auto switch_type = device_ctx.rr_switch_inf[kv.first].type();

VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)",
inode, kv.second, to_node, kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]);
VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_graph: node %d has %d redundant connections to node %d of switch type %d (%s)",
inode, kv.second, to_node, kv.first, SWITCH_TYPE_STRINGS[size_t(switch_type)]);
}
}
}

Expand Down
66 changes: 39 additions & 27 deletions vpr/src/route/rr_graph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1455,10 +1455,10 @@ static void build_rr_sinks_sources(const int i,
/* Connect IPINS to SINKS and initialize OPINS */
//We loop through all the pin locations on the block to initialize the IPINs/OPINs,
//and hook-up the IPINs to sinks.
for (int width_offset = 0; width_offset < type->width; ++width_offset) {
for (int height_offset = 0; height_offset < type->height; ++height_offset) {
for (e_side side : {TOP, BOTTOM, LEFT, RIGHT}) {
for (int ipin = 0; ipin < num_pins; ++ipin) {
for (int ipin = 0; ipin < num_pins; ++ipin) {
for (e_side side : SIDES) {
for (int width_offset = 0; width_offset < type->width; ++width_offset) {
for (int height_offset = 0; height_offset < type->height; ++height_offset) {
if (type->pinloc[width_offset][height_offset][side][ipin]) {
int inode;
int iclass = pin_class[ipin];
Expand All @@ -1467,40 +1467,50 @@ static void build_rr_sinks_sources(const int i,
//Connect the input pin to the sink
inode = get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, IPIN, ipin, side);

int to_node = get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass);

//Add info about the edge to be created
rr_edges_to_create.emplace_back(inode, to_node, delayless_switch);
/* Input pins are uniquified, we may not always find one */
if (OPEN != inode) {
int to_node = get_rr_node_index(L_rr_node_indices, i, j, SINK, iclass);

VTR_ASSERT(inode >= 0);
L_rr_node[inode].set_cost_index(IPIN_COST_INDEX);
L_rr_node[inode].set_type(IPIN);
//Add info about the edge to be created
rr_edges_to_create.emplace_back(inode, to_node, delayless_switch);

VTR_ASSERT(inode >= 0);
L_rr_node[inode].set_cost_index(IPIN_COST_INDEX);
L_rr_node[inode].set_type(IPIN);
}
} else {
VTR_ASSERT(class_inf[iclass].type == DRIVER);
//Initialize the output pin
// Note that we leave it's out-going edges unconnected (they will be hooked up to global routing later)
inode = get_rr_node_index(L_rr_node_indices, i + width_offset, j + height_offset, OPIN, ipin, side);

//Initially left unconnected
VTR_ASSERT(inode >= 0);
L_rr_node[inode].set_cost_index(OPIN_COST_INDEX);
L_rr_node[inode].set_type(OPIN);
/* Output pins may not exist on some sides, we may not always find one */
if (OPEN != inode) {
//Initially left unconnected
VTR_ASSERT(inode >= 0);
L_rr_node[inode].set_cost_index(OPIN_COST_INDEX);
L_rr_node[inode].set_type(OPIN);
}
}

/* Common to both DRIVERs and RECEIVERs */
L_rr_node[inode].set_capacity(1);
float R = 0.;
float C = 0.;
L_rr_node[inode].set_rc_index(find_create_rr_rc_data(R, C));
L_rr_node[inode].set_ptc_num(ipin);

//Note that we store the grid tile location and side where the pin is located,
//which greatly simplifies the drawing code
L_rr_node[inode].set_coordinates(i + width_offset, j + height_offset, i + width_offset, j + height_offset);
L_rr_node[inode].set_side(side);

VTR_ASSERT(type->pinloc[width_offset][height_offset][L_rr_node[inode].side()][L_rr_node[inode].pin_num()]);
if (OPEN != inode) {
L_rr_node[inode].set_capacity(1);
float R = 0.;
float C = 0.;
L_rr_node[inode].set_rc_index(find_create_rr_rc_data(R, C));
L_rr_node[inode].set_ptc_num(ipin);

//Note that we store the grid tile location and side where the pin is located,
//which greatly simplifies the drawing code
//For those pins located on multiple sides, we save the rr node index
//for the pin on all sides at which it exists
//As such, multipler driver problem can be avoided.
L_rr_node[inode].set_coordinates(i + width_offset, j + height_offset, i + width_offset, j + height_offset);
L_rr_node[inode].set_side(side);

VTR_ASSERT(type->pinloc[width_offset][height_offset][L_rr_node[inode].side()][L_rr_node[inode].pin_num()]);
}
}
}
}
Expand Down Expand Up @@ -2478,6 +2488,8 @@ std::string describe_rr_node(int inode) {
}

msg += vtr::string_fmt(" capacity: %d", rr_node.capacity());
msg += vtr::string_fmt(" fan-in: %d", rr_node.fan_in());
msg += vtr::string_fmt(" fan-out: %d", rr_node.num_edges());

return msg;
}
Expand Down
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