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Fix timing cost consistency check bug #1417

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Merged
merged 2 commits into from
Jul 13, 2020
Merged

Fix timing cost consistency check bug #1417

merged 2 commits into from
Jul 13, 2020

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Bill-hbrhbr
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Related Issue

#1402

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@Bill-hbrhbr Bill-hbrhbr self-assigned this Jul 10, 2020
@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code VPR VPR FPGA Placement & Routing Tool labels Jul 10, 2020
@Bill-hbrhbr
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@litghost Feel free to follow up if this fix doesn't work. I have yet to gather the QoR results, so this PR will not be merged immediately. It's only a couple lines of code.

@Bill-hbrhbr
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VTR benchmarks: https://drive.google.com/file/d/1Bcr1yicJg7szKzdFXzLy_FBh_Mzjc3Eh/view?usp=sharing
Titan benchmarks: https://drive.google.com/file/d/1J22fK7TvPfveEDXmw0yA8PBiS6sVLHiv/view?usp=sharing
Slightly faster in place_time with no change to results.

litghost
litghost approved these changes Jul 13, 2020
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LGTM. We still have the other assertion violation, but they may be unrelated issues.

@Bill-hbrhbr Bill-hbrhbr merged commit 82c0210 into verilog-to-routing:master Jul 13, 2020
@Bill-hbrhbr Bill-hbrhbr deleted the placer_timing_cost_consistency_check branch July 13, 2020 19:18
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@litghost litghost litghost approved these changes

@kmurray kmurray Awaiting requested review from kmurray

@vaughnbetz vaughnbetz Awaiting requested review from vaughnbetz

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@Bill-hbrhbr @litghost