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Adding documentation for two stage clock routing cmd line option #1103

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Merged
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Apr 13, 2020
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Adding documentation for two stage clock routing cmd line option #1103

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Adding documentation two stage clock routing cmd line option
mustafabbas Feb 3, 2020
fcdc605
Docs: Updating the two_stage_routing option
mustafabbas Feb 10, 2020
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8 changes: 5 additions & 3 deletions doc/src/vpr/command_line_usage.rst
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Expand Up @@ -182,12 +182,14 @@ General Options

**Default:** ``ideal``

.. option:: --two_stage_clock_routing
.. option:: --two_stage_clock_routing {on | off}

Routes clock nets in two stages using a dedicated clock network.

* First stage: From the net source (e.g. an I/O pin) to a dedicated clock network source (e.g. center of chip)
* Second stage: From the clock network source to net sinks.
* First stage: From the net source (e.g. an I/O pin) to a dedicated clock network root (e.g. center of chip)
* Second stage: From the clock network root to net sinks.

Note this option only works when specifying a clock architecture, see :ref:`Clock Architecture Format <clock_architecture_format>`; it does not work when reading a routing resource graph (i.e. :option:`--read_rr_graph`).
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Note dead clock architecture link until #1104 is merged


**Default:** ``off``

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