Support pre-nehalem processors

[asaadmohammed74]

hello, its my first time using cranelift as a back-end, my first hello world program which is just a cargo new project,
crashes with SIGILL

`
build

cg_clif_dir/build/cargo.sh b
`

this is lldb output
`

• thread Implement a subset of all intrinsics #1, name = 'hello_world', stop reason = signal SIGILL: illegal instruction operand
  frame #0: 0x0000555555655f96 hello_worldcore::alloc::layout::Layout::from_size_align::h6048d467bfec8bb4 + 8 hello_worldcore::alloc::layout::Layout::from_size_align::h6048d467bfec8bb4:
  -> 0x555555655f96 <+8>: popcntq %rsi, %rax
  0x555555655f9b <+13>: movl $0x1, %ecx
  0x555555655fa0 <+18>: cmpl %ecx, %eax
  0x555555655fa2 <+20>: jne 0x55555565600d ; <+127> at layout.rs:63:20
  (lldb) bt
• thread Implement a subset of all intrinsics #1, name = 'hello_world', stop reason = signal SIGILL: illegal instruction operand
  • frame #0: 0x0000555555655f96 hello_worldcore::alloc::layout::Layout::from_size_align::h6048d467bfec8bb4 + 8 frame #1: 0x0000555555655ebe hello_worldcore::alloc::layout::Layout::pad_to_align::h3568c8d4bff4febc at nonzero.rs:148:1
    frame Support rust-call abi for closures #2: 0x0000555555656117 hello_worldcore::alloc::layout::Layout::array::h015c7a99e7b0bc37 at layout.rs:394:14 frame #3: 0x000055555565daf6 hello_worldalloc::raw_vec::RawVec$LT$T$C$A$GT$::allocate_in::hd048b82a60ccc1a8 + 43
    frame Dependabot couldn't find a Cargo.toml for this project #4: 0x000055555556c7eb hello_world_$LT$T$u20$as$u20$alloc..slice..hack..ConvertVec$GT$::to_vec::h95d9fe7b35c0ffb0 at mod.rs:117:22 frame #5: 0x000055555557ee5c hello_worldstd::rt::lang_start_internal::h55442e27331b7102 at rt.rs:44:39
    frame Properly implement checked binops #6: 0x00005555555671d9 hello_worldstd::rt::lang_start::hd60cecbcdf6bd999 at rt.rs:66:9 frame #7: 0x0000555555567268 hello_worldmain + 29
    frame Don't hardcode usize being 64 bit #8: 0x00007ffff7db4b25 libc.so.6__libc_start_main + 213 frame #9: 0x000055555556706e hello_world_start + 46
    `

my cpu is core 2 due T7300

[bjorn3]

The popcnt instruction seems to have been introduced with nehalem (https://github.com/bytecodealliance/wasmtime/blob/5c1d728e3ae8ee7aa329e294999a2c3086b21676/cranelift/codegen/meta/src/isa/x86/settings.rs#L108-L111). Your processor predates this introduction.

You could try disabling the nehalem preset here: https://github.com/bjorn3/rustc_codegen_cranelift/blob/341a4863fabe8c67b1b72c6d3183ee824878f950/src/lib.rs#L338 It is possible that compilation will fail though. If it fails removing this line may help: https://github.com/bjorn3/rustc_codegen_cranelift/blob/341a4863fabe8c67b1b72c6d3183ee824878f950/src/common.rs#L73

If disabling the nehalem preset fixes the problem, I would like to keep this issue open as tracking issue for pre-nehalem processors.

[asaadmohammed74]

The popcnt instruction seems to have been introduced with nehalem (https://github.com/bytecodealliance/wasmtime/blob/5c1d728e3ae8ee7aa329e294999a2c3086b21676/cranelift/codegen/meta/src/isa/x86/settings.rs#L108-L111). Your processor predates this introduction.

You could try disabling the nehalem preset here:

https://github.com/bjorn3/rustc_codegen_cranelift/blob/341a4863fabe8c67b1b72c6d3183ee824878f950/src/lib.rs#L338

It is possible that compilation will fail though. If it fails removing this line may help:
https://github.com/bjorn3/rustc_codegen_cranelift/blob/341a4863fabe8c67b1b72c6d3183ee824878f950/src/common.rs#L73

If disabling the nehalem preset fixes the problem, I would like to keep this issue open as tracking issue for pre-nehalem processors.

commenting the nehalem line solved the problem, thank you

[bjorn3]

(deleted a duplicate comment)

[bjorn3]

cg_clif should now compile against the same target cpu as the LLVM backend would. I haven't tested if it doesn't accidentally use any newer instruction though.