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Fix SPI mode and bit order settings #13

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Merged
merged 2 commits into from
Jul 3, 2023
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trevor-makes
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@trevor-makes trevor-makes commented Jun 28, 2023

#12
The logical not in this line makes the mask 0 and wipes out the earlier settings. This should be a bitwise not, but even so the 0xFF would also mask off the SSLA bits b6-b4 and half of the SPB bits b9-b8. Changing 0xFF to 3 will clear just the BRDV bits b3-b2.

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CLAassistant commented Jun 28, 2023

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All committers have signed the CLA.

@MrYsLab
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MrYsLab commented Jun 30, 2023

I verified the fix using an ADXL345, and it works!
Thanks.

@facchinm
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facchinm commented Jul 3, 2023

Thank you so much for the fix!

@facchinm facchinm merged commit fbb44b6 into arduino:main Jul 3, 2023
maidnl pushed a commit that referenced this pull request Jul 4, 2023
Refactor SPI module a bit (configuration code especially).
cristidragomir97 pushed a commit to cristidragomir97/ArduinoCore-renesas that referenced this pull request May 20, 2024
Refactor SPI module a bit (configuration code especially).

Former-commit-id: d29cb4e
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4 participants