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Logical netlist writer#9

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Commits on Dec 21, 2021

• libs: arch: move common functions to util and check source files

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• libs: arch: interchange: add logical blocks and physical tile parsing

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• vpr: tests: improve interchange tests

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• libs: arch: interchange: improve bel to cell mapping

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• libs: arch: fix multiple sites and rr graph gen

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• libs: arch: interchange: fix IO pads reading

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• libs: arch: interchange: add workarounds for RR graph generation

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• vpr: test: interchange: fix grid width and height

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• vpr: base: remove cStr() casts from interchange netlist reader

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• libs: arch: interchange: fix and enhance to start reading in xc7 arch

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• libs: arch: interchange: allow cascading routing bels

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• vpr: pack: allow pins to have name starting with integer

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• libs: arch: interchange : allow inout ports in bels connected to pads

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• vpr: base: interchange: netlist: add c-style init and fixed bug

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• libs: arch: interchange: add pack pattern propagation

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• libs: arch: interchange: clean and add in-code comments

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• vpr: test: adjust grid layout test as NULL tile is not in the grid

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Commits on Dec 22, 2021

• Added reading LUT elements from FPGA interchange

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• libs: arch: interchange: fix luts that have additional pins

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Commits on Dec 23, 2021

• Initial writer implementation. Blind writing of cell declarations (models)

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• Reworked cell declarations, added serializing cell instances, no nets yet

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• Added serialization of nets. Apart from possible bugs the only thing missing is property maps

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• Added conversion of all .input/.output instances to a single top-level cell instance. No net connections yet

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• Added top-level port connections

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• Added a command line option controlling circuit netlist writeout

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• Added serialization of property maps

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• Code formatting

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