Added serialization of property maps

Signed-off-by: Maciej Kurc <[email protected]>

Author: mkurc-ant

vpr/src/base/write_interchange_netlist.cpp

@@ -33,10 +33,10 @@ class NetlistBuilder {
         logical_netlist.setName(netlist_.netlist_name());
 
         // Build and serialize cell library
-        build_library(logical_netlist);
+        buildLibrary(logical_netlist);
 
         // Build and serialize the netlist
-        build_netlist(logical_netlist);
+        buildNetlist(logical_netlist);
 
         // Serialize the string list
         auto strList = logical_netlist.initStrList(strings_.size());
@@ -49,12 +49,14 @@ class NetlistBuilder {
 
 protected:
 
+    typedef std::unordered_map<std::string, std::string> Properties;
+
     struct Port {
         uint32_t index;
         Direction dir;
         bool isBus;
         uint32_t bitLo, bitHi;
-        // TODO: Property map
+        Properties properties;
     };
 
     struct PortInstance {
@@ -66,20 +68,20 @@ class NetlistBuilder {
 
     struct Net {
         std::unordered_map<std::string, std::vector<PortInstance>> ports;
-        // TODO: Property map
+        Properties properties;
     };
 
     struct CellDeclaration {
         uint32_t index;
         std::vector<std::string> ports;
-        // TODO: Property map
+        Properties properties;
     };
 
     struct CellInstance {
         uint32_t index;
         std::string type;
         std::string name;
-        // TODO: Property map
+        Properties properties;
     };
 
     struct Cell {
@@ -101,7 +103,7 @@ class NetlistBuilder {
 
     // ....................................................
 
-    void build_library (LogicalNetlist::Netlist::Builder& logical_netlist) {
+    void buildLibrary (LogicalNetlist::Netlist::Builder& logical_netlist) {
 
         // Collect models and their ports
         std::unordered_map<std::string, const t_model*> models;
@@ -132,7 +134,9 @@ class NetlistBuilder {
                 bus.setBusStart(port.bitLo);
                 bus.setBusEnd(port.bitHi);
             }
-            // TODO: Prop map
+
+            auto propMap = portList[port.index].initPropMap();
+            buildPropertyMap(propMap, port.properties);
         }
 
         // Serialize cell definitions
@@ -147,11 +151,13 @@ class NetlistBuilder {
                 const auto& port = ports_.at(std::make_pair(it.first, decl.ports[i]));
                 ports.set(i, port.index);
             }
-            // TODO: Prop map
+
+            auto propMap = cellDecls[decl.index].initPropMap();
+            buildPropertyMap(propMap, decl.properties);
         }
     }
 
-    void build_netlist (LogicalNetlist::Netlist::Builder& logical_netlist) {
+    void buildNetlist (LogicalNetlist::Netlist::Builder& logical_netlist) {
 
         // Add cell instances
         for (const auto blk : netlist_.blocks()) {
@@ -179,7 +185,9 @@ class NetlistBuilder {
             instList[inst.index].setName(strId(inst.name));
             instList[inst.index].setView(strId("netlist"));
             instList[inst.index].setCell(cellDeclarations_.at(inst.type).index);
-            // TODO: Prop map
+
+            auto propMap = instList[inst.index].initPropMap();
+            buildPropertyMap(propMap, inst.properties);
         }
 
         // Serialize top-level instance
@@ -276,7 +284,9 @@ class NetlistBuilder {
                     }
                 }
 
-                // TODO: prop map
+                // Property map
+                auto propMap = nets[netIndex].initPropMap();
+                buildPropertyMap(propMap, net.properties);
 
                 // Next net
                 netIndex++;
@@ -287,6 +297,17 @@ class NetlistBuilder {
         }
     }
 
+    void buildPropertyMap (::LogicalNetlist::Netlist::PropertyMap::Builder& propertyMap, const Properties& properties) {
+        auto entries = propertyMap.initEntries(properties.size());
+        size_t index = 0;
+
+        for (const auto& it : properties) {
+            entries[index].setKey(strId(it.first));
+            entries[index].setTextValue(strId(it.second)); // FIXME: VPR keeps all attributes / parameters as strings
+            index++;
+        }
+    }
+
     // ....................................................
 
     static bool isIoModel (const char* str) {
@@ -315,8 +336,6 @@ class NetlistBuilder {
         // Create a new cell declaration from the model
         CellDeclaration decl;
 
-        // TODO: Property map
-
         // Collect ports
         for(t_model_ports* p=model->inputs; p; p=p->next) {
             addPort(model->name, p, Direction::INPUT);
@@ -327,6 +346,13 @@ class NetlistBuilder {
             decl.ports.push_back(p->name);
         }
 
+        // Cell definition properties
+        // FIXME: Should those information be written as properties? What
+        // should be the mapping of those attributes to interchange properties ?
+        if (model->never_prune) {
+            decl.properties["never_prune"] = "1";
+        }
+
         // Add it
         decl.index = cellDeclarations_.size();
         cellDeclarations_.emplace(std::make_pair(model->name, decl));
@@ -354,6 +380,16 @@ class NetlistBuilder {
             port.bitHi = 0;
         }
 
+        // Port properties
+        // FIXME: Should those information be written as properties? What
+        // should be the mapping of those attributes to interchange properties ?
+        if (modelPort->is_clock) {
+            port.properties["is_clock"] = "1";
+        }
+        if (modelPort->is_non_clock_global) {
+            port.properties["is_non_clock_global"] = "1";
+        }
+
         // Add the port 
         port.index = ports_.size();
         ports_.emplace(std::make_pair(std::make_pair(modelName, modelPort->name), port));
@@ -368,7 +404,24 @@ class NetlistBuilder {
         inst.name = netlist_.block_name(block);
         inst.type = model->name;
 
-        // TODO: Property map
+        // Collect attributes and parameters
+        auto addProperty = [&](const std::pair<std::string, std::string>& prop) {
+            if (inst.properties.count(prop.first)) {
+                VTR_LOG_WARN("Duplicate property '%s'='%s' of cell instance '%s'\n",
+                    prop.first.c_str(), prop.second.c_str(), inst.name.c_str());
+            } else {
+                inst.properties.insert(prop);
+            }
+        };
+
+        // FIXME: The FPGA Interchange logical netlist format does not
+        // differentiate between attributes and parameters.
+        for (const auto& it : netlist_.block_attrs(block)) {
+            addProperty(it);
+        }
+        for (const auto& it : netlist_.block_params(block)) {
+            addProperty(it);
+        }
 
         // Add the cell instance
         inst.index = cellInstances_.size();