Added a command line option controlling circuit netlist writeout

Signed-off-by: Maciej Kurc <[email protected]>

Author: mkurc-ant

vpr/src/base/read_circuit.cpp

@@ -12,6 +12,8 @@
 #include "vtr_path.h"
 #include "vtr_time.h"
 
+#include "read_options.h"
+
 static void process_circuit(AtomNetlist& netlist,
                             e_const_gen_inference const_gen_inference_method,
                             bool should_absorb_buffers,
@@ -23,9 +25,11 @@ static void process_circuit(AtomNetlist& netlist,
 
 static void show_circuit_stats(const AtomNetlist& netlist);
 
-AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch) {
+AtomNetlist read_and_process_circuit(const t_options& options, t_vpr_setup& vpr_setup, t_arch& arch) {
     // Options
-    const char* circuit_file = vpr_setup.PackerOpts.circuit_file_name.c_str();
+    const char* rd_circuit_file = vpr_setup.PackerOpts.circuit_file_name.c_str();
+    const std::string& wr_circuit_file = options.write_circuit_file;
+    e_circuit_format circuit_format = options.circuit_format;
     const t_model* user_models = vpr_setup.user_models;
     const t_model* library_models = vpr_setup.library_models;
     e_const_gen_inference const_gen_inference = vpr_setup.NetlistOpts.const_gen_inference;
@@ -37,16 +41,16 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu
     bool verbosity = vpr_setup.NetlistOpts.netlist_verbosity;
 
     if (circuit_format == e_circuit_format::AUTO) {
-        auto name_ext = vtr::split_ext(circuit_file);
+        auto name_ext = vtr::split_ext(rd_circuit_file);
 
-        VTR_LOGV(verbosity, "Circuit file: %s\n", circuit_file);
+        VTR_LOGV(verbosity, "Circuit file: %s\n", rd_circuit_file);
         if (name_ext[1] == ".blif") {
             circuit_format = e_circuit_format::BLIF;
         } else if (name_ext[1] == ".eblif") {
             circuit_format = e_circuit_format::EBLIF;
         } else {
             VPR_FATAL_ERROR(VPR_ERROR_ATOM_NETLIST, "Failed to determine file format for '%s' expected .blif or .eblif extension",
-                            circuit_file);
+                            rd_circuit_file);
         }
     }
 
@@ -57,15 +61,15 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu
         switch (circuit_format) {
             case e_circuit_format::BLIF:
             case e_circuit_format::EBLIF:
-                netlist = read_blif(circuit_format, circuit_file, user_models, library_models);
+                netlist = read_blif(circuit_format, rd_circuit_file, user_models, library_models);
                 break;
             case e_circuit_format::FPGA_INTERCHANGE:
-                netlist = read_interchange_netlist(circuit_file, arch);
+                netlist = read_interchange_netlist(rd_circuit_file, arch);
                 break;
             default:
                 VPR_FATAL_ERROR(VPR_ERROR_ATOM_NETLIST,
                                 "Unable to identify circuit file format for '%s'. Expect [blif|eblif|fpga-interchange]!\n",
-                                circuit_file);
+                                rd_circuit_file);
                 break;
         }
     }
@@ -87,10 +91,15 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setu
         print_netlist_as_blif(getEchoFileName(E_ECHO_ATOM_NETLIST_CLEANED), netlist);
     }
 
-    show_circuit_stats(netlist);
+    // Write FPGA interchange logical netlist.
+    // TODO: Possibly allow writing BLIF/ELBIF via --write_circuit too
+    // TODO: Possibly make separate options for read and write circuit format
+    if (circuit_format == e_circuit_format::FPGA_INTERCHANGE && !wr_circuit_file.empty()) {
+        vtr::ScopedStartFinishTimer t("Write circuit");
+        write_interchange_netlist(wr_circuit_file, netlist, arch);
+    }
 
-    // FIXME: Add option
-    write_interchange_netlist("logical.netlist", netlist, arch);
+    show_circuit_stats(netlist);
 
     return netlist;
 }

vpr/src/base/read_circuit.h

@@ -4,12 +4,14 @@
 #include "atom_netlist_fwd.h"
 #include "vpr_types.h"
 
+struct t_options;
+
 enum class e_circuit_format {
     AUTO,            ///<Infer from file extension
     BLIF,            ///<Strict structural BLIF
     EBLIF,           ///<Structural blif with extensions
     FPGA_INTERCHANGE ///<FPGA Interhange logical netlis format
 };
 
-AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch);
+AtomNetlist read_and_process_circuit(const t_options& options, t_vpr_setup& vpr_setup, t_arch& arch);
 #endif

vpr/src/base/read_options.cpp

@@ -1486,6 +1486,10 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
         .help("Writes the placement delay lookup to the specified file.")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
+    file_grp.add_argument(args.write_circuit_file, "--write_circuit")
+        .help("Writes the circuit netlist used for placement and routing to the specified file.")
+        .show_in(argparse::ShowIn::HELP_ONLY);
+
     file_grp.add_argument(args.out_file_prefix, "--outfile_prefix")
         .help("Prefix for output files")
         .show_in(argparse::ShowIn::HELP_ONLY);

vpr/src/base/read_options.h

@@ -36,6 +36,8 @@ struct t_options {
     argparse::ArgValue<std::string> write_router_lookahead;
     argparse::ArgValue<std::string> read_router_lookahead;
 
+    argparse::ArgValue<std::string> write_circuit_file;
+
     /* Stage Options */
     argparse::ArgValue<bool> do_packing;
     argparse::ArgValue<bool> do_placement;

vpr/src/base/vpr_api.cpp

@@ -313,7 +313,7 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a
 
     /* Read blif file and sweep unused components */
     auto& atom_ctx = g_vpr_ctx.mutable_atom();
-    atom_ctx.nlist = read_and_process_circuit(options->circuit_format, *vpr_setup, *arch);
+    atom_ctx.nlist = read_and_process_circuit(*options, *vpr_setup, *arch);
 
     if (vpr_setup->PowerOpts.do_power) {
         //Load the net activity file for power estimation

vpr/src/base/write_interchange_netlist.cpp

@@ -473,7 +473,7 @@ class NetlistBuilder {
 
 
 void write_interchange_netlist (
-    const char* ic_netlist_file,
+    const std::string& ic_netlist_file,
     const AtomNetlist& netlist,
     const t_arch& arch)
 {
@@ -491,7 +491,7 @@ void write_interchange_netlist (
     kj::ArrayPtr<kj::byte> bytes = words.asBytes();
 
     // Write
-    gzFile fp = gzopen(ic_netlist_file, "w");
+    gzFile fp = gzopen(ic_netlist_file.c_str(), "w");
     VTR_ASSERT(fp != Z_NULL);
 
     z_size_t res = gzwrite(fp, &bytes[0], bytes.size());

vpr/src/base/write_interchange_netlist.h

@@ -6,7 +6,7 @@
 #include "vpr_types.h"
 
 void write_interchange_netlist (
-    const char* ic_netlist_file,
+    const std::string& ic_netlist_file,
     const AtomNetlist& netlist,
     const t_arch& arch
 );

vpr/test/test_interchange_netlist.cpp

@@ -1,5 +1,6 @@
 #include "catch2/catch_test_macros.hpp"
 
+#include "argparse_value.hpp"
 #include "read_circuit.h"
 #include "read_fpga_interchange_arch.h"
 #include "arch_util.h"
@@ -25,9 +26,12 @@ TEST_CASE("read_interchange_netlist", "[vpr]") {
     vpr_setup.library_models = arch.model_library;
     vpr_setup.PackerOpts.circuit_file_name = "lut.netlist";
 
+    t_options options;
+    options.circuit_format.set(e_circuit_format::FPGA_INTERCHANGE, argparse::Provenance::SPECIFIED);
+
     /* Read blif file and sweep unused components */
     auto& atom_ctx = g_vpr_ctx.mutable_atom();
-    atom_ctx.nlist = read_and_process_circuit(e_circuit_format::FPGA_INTERCHANGE, vpr_setup, arch);
+    atom_ctx.nlist = read_and_process_circuit(options, vpr_setup, arch);
 }
 
 } // namespace