@@ -256,7 +256,7 @@ struct ArchReader {
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// Bel Cell mappings
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std::unordered_map<uint32_t , std::vector<t_bel_cell_mapping>> bel_cell_mappings_;
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- std::unordered_map<std::string, int > SegmentName_to_SegmentIdx ;
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+ std::unordered_map<std::string, int > segment_name_to_segment_idx ;
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// Utils
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std::string str (int idx) {
@@ -1148,14 +1148,12 @@ struct ArchReader {
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for (auto tile : tileTypeList) {
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t_physical_tile_type ptype;
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auto name = str (tile.getName ());
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-
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- if (name == std::string (" NULL" ))
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+ if (name == EMPTY.name )
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continue ;
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-
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ptype.name = vtr::strdup (name.c_str ());
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ptype.index = ++index;
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ptype.width = ptype.height = ptype.area = 1 ;
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- ptype.capacity = 1 ;
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+ ptype.capacity = 0 ;
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process_sub_tiles (ptype, tile);
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@@ -1184,17 +1182,18 @@ struct ArchReader {
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auto site = siteTypeList[site_in_tile.getPrimaryType ()];
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auto pins_to_wires = site_in_tile.getPrimaryPinsToTileWires ();
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- sub_tile.index = 0 ;
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+ sub_tile.index = type. capacity ;
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sub_tile.name = vtr::strdup (str (site.getName ()).c_str ());
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- sub_tile.capacity .set (0 , 0 );
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+ sub_tile.capacity .set (type.capacity , type.capacity );
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+ type.capacity ++;
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int port_idx = 0 ;
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int abs_first_pin_idx = 0 ;
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int icount = 0 ;
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int ocount = 0 ;
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- std::unordered_map<std::string, std::string> PortName_to_WireName ;
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- int idx = 0 ;
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+ std::unordered_map<std::string, std::string> port_name_to_wire_name ;
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+ int idx = 0 ;
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for (auto dir : {LogicalNetlist::Netlist::Direction::INPUT, LogicalNetlist::Netlist::Direction::OUTPUT}) {
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int port_idx_by_type = 0 ;
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for (auto pin : site.getPins ()) {
@@ -1205,12 +1204,12 @@ struct ArchReader {
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port.name = vtr::strdup (str (pin.getName ()).c_str ());
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- PortName_to_WireName [std::string (port.name )] = str (pins_to_wires[idx++]);
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+ port_name_to_wire_name [std::string (port.name )] = str (pins_to_wires[idx++]);
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port.equivalent = PortEquivalence::NONE;
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port.num_pins = 1 ;
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- sub_tile.sub_tile_to_tile_pin_indices .push_back (port_idx);
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+ sub_tile.sub_tile_to_tile_pin_indices .push_back (type. num_pins + port_idx);
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port.index = port_idx++;
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port.absolute_first_pin_index = abs_first_pin_idx++;
@@ -1232,14 +1231,14 @@ struct ArchReader {
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}
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auto pins_size = site.getPins ().size ();
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- sub_tile.num_phy_pins += pins_size * type. capacity ;
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- type.num_pins += pins_size * type. capacity ;
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+ sub_tile.num_phy_pins += pins_size;
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+ type.num_pins += pins_size;
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type.num_inst_pins += pins_size;
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type.num_input_pins += icount;
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type.num_output_pins += ocount;
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- type.num_receivers += icount * type. capacity ;
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- type.num_drivers += ocount * type. capacity ;
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+ type.num_receivers += icount;
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+ type.num_drivers += ocount;
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type.pin_width_offset .resize (type.num_pins , 0 );
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type.pin_height_offset .resize (type.num_pins , 0 );
@@ -1272,7 +1271,7 @@ struct ArchReader {
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for (const auto & port : sub_tile.ports ) {
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t_fc_specification fc_spec;
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- fc_spec.seg_index = SegmentName_to_SegmentIdx[PortName_to_WireName [std::string (port.name )]];
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+ fc_spec.seg_index = segment_name_to_segment_idx[port_name_to_wire_name [std::string (port.name )]];
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// Apply type and defaults
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if (port.type == IN_PORT) {
@@ -1355,8 +1354,8 @@ struct ArchReader {
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t_grid_def grid_def;
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grid_def.width = grid_def.height = 0 ;
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for (auto tile : tileList) {
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- grid_def.width = std::max (grid_def.width , tile.getCol () + 1 );
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- grid_def.height = std::max (grid_def.height , tile.getRow () + 1 );
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+ grid_def.width = std::max (grid_def.width , tile.getCol ());
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+ grid_def.height = std::max (grid_def.height , tile.getRow ());
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}
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grid_def.grid_type = GridDefType::FIXED;
@@ -1566,7 +1565,7 @@ struct ArchReader {
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arch_->Segments [index].sb .resize (2 );
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arch_->Segments [index].sb [0 ] = true ;
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arch_->Segments [index].sb [1 ] = true ;
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- SegmentName_to_SegmentIdx [str (i)] = index;
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+ segment_name_to_segment_idx [str (i)] = index;
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++index;
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}
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}
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