Skip to content

Commit 3190567

Browse files
mtdudekmtdudek
committed
Fix pb_type_port structure
Remove unnecessary c_str() Signed-off-by: Maciej Dudek <[email protected]>
1 parent 93d6da2 commit 3190567

File tree

7 files changed

+59
-45
lines changed

7 files changed

+59
-45
lines changed

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -226,6 +226,9 @@ struct ArchReader {
226226

227227
process_models();
228228
process_device();
229+
process_layout();
230+
process_switches();
231+
process_segments();
229232

230233
process_blocks();
231234
process_tiles();
@@ -234,9 +237,6 @@ struct ArchReader {
234237
SyncModelsPbTypes(arch_, ltypes_);
235238
check_models(arch_);
236239

237-
process_layout();
238-
process_switches();
239-
process_segments();
240240
}
241241

242242
private:
@@ -256,6 +256,8 @@ struct ArchReader {
256256
// Bel Cell mappings
257257
std::unordered_map<uint32_t, std::vector<t_bel_cell_mapping>> bel_cell_mappings_;
258258

259+
std::unordered_map<std::string, int> SegmentName_to_SegmentIdx;
260+
259261
// Utils
260262
std::string str(int idx) {
261263
return arch_->interned_strings[idx].get(&arch_->strings);
@@ -1180,6 +1182,7 @@ struct ArchReader {
11801182
t_sub_tile sub_tile;
11811183

11821184
auto site = siteTypeList[site_in_tile.getPrimaryType()];
1185+
auto pins_to_wires = site_in_tile.getPrimaryPinsToTileWires();
11831186

11841187
sub_tile.index = 0;
11851188
sub_tile.name = vtr::strdup(str(site.getName()).c_str());
@@ -1189,6 +1192,9 @@ struct ArchReader {
11891192
int abs_first_pin_idx = 0;
11901193
int icount = 0;
11911194
int ocount = 0;
1195+
1196+
std::unordered_map<std::string, std::string> PortName_to_WireName;
1197+
int idx = 0;
11921198
for (auto dir : {LogicalNetlist::Netlist::Direction::INPUT, LogicalNetlist::Netlist::Direction::OUTPUT}) {
11931199
int port_idx_by_type = 0;
11941200
for (auto pin : site.getPins()) {
@@ -1198,6 +1204,9 @@ struct ArchReader {
11981204
t_physical_tile_port port;
11991205

12001206
port.name = vtr::strdup(str(pin.getName()).c_str());
1207+
1208+
PortName_to_WireName[std::string(port.name)] = str(pins_to_wires[idx++]);
1209+
12011210
port.equivalent = PortEquivalence::NONE;
12021211
port.num_pins = 1;
12031212

@@ -1207,6 +1216,9 @@ struct ArchReader {
12071216
port.absolute_first_pin_index = abs_first_pin_idx++;
12081217
port.port_index_by_type = port_idx_by_type++;
12091218

1219+
port.is_clock = false;
1220+
port.is_non_clock_global = false;
1221+
12101222
if (dir == LogicalNetlist::Netlist::Direction::INPUT) {
12111223
port.type = IN_PORT;
12121224
icount++;
@@ -1260,7 +1272,7 @@ struct ArchReader {
12601272
for (const auto& port : sub_tile.ports) {
12611273
t_fc_specification fc_spec;
12621274

1263-
fc_spec.seg_index = 0;
1275+
fc_spec.seg_index = SegmentName_to_SegmentIdx[PortName_to_WireName[std::string(port.name)]];
12641276

12651277
//Apply type and defaults
12661278
if (port.type == IN_PORT) {
@@ -1539,8 +1551,8 @@ struct ArchReader {
15391551
arch_->Segments[index].name = str(i);
15401552
arch_->Segments[index].length = 1;
15411553
arch_->Segments[index].frequency = 1;
1542-
arch_->Segments[index].Rmetal = 0;
1543-
arch_->Segments[index].Cmetal = 0;
1554+
arch_->Segments[index].Rmetal = 1e2;
1555+
arch_->Segments[index].Cmetal = 1e-15;
15441556
arch_->Segments[index].parallel_axis = BOTH_AXIS;
15451557

15461558
// TODO: Only bi-directional segments are created, but it the interchange format
@@ -1554,6 +1566,7 @@ struct ArchReader {
15541566
arch_->Segments[index].sb.resize(2);
15551567
arch_->Segments[index].sb[0] = true;
15561568
arch_->Segments[index].sb[1] = true;
1569+
SegmentName_to_SegmentIdx[str(i)] = index;
15571570
++index;
15581571
}
15591572
}

‎vpr/src/base/read_interchange_netlist.cpp

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ struct NetlistReader {
8787
auto top_cell_decl = nr_.getCellDecls()[top_cell_instance_.getCell()];
8888
for (auto top_port : top_cell_decl.getPorts()) {
8989
auto port = nr_.getPortList()[top_port];
90-
auto name = std::string(str_list[port.getName()].cStr());
90+
auto name = str_list[port.getName()];
9191
auto dir = port.getDir();
9292

9393
int bus_size, start_bit;
@@ -96,7 +96,7 @@ struct NetlistReader {
9696
for (int bit = start_bit; bit < start_bit + bus_size; bit++) {
9797
auto port_name = name;
9898
if (bus_size > 1)
99-
port_name = name + "[" + std::to_string(bit) + "]";
99+
port_name = std::string(name) + "[" + std::to_string(bit) + "]";
100100

101101
AtomBlockId blk_id;
102102
AtomPortId port_id;
@@ -145,7 +145,7 @@ struct NetlistReader {
145145
bool is_lut;
146146
int width;
147147
std::string init_param;
148-
std::tie(is_lut, width, init_param) = is_lut_cell(str_list[cell.getName()].cStr());
148+
std::tie(is_lut, width, init_param) = is_lut_cell(str_list[cell.getName()]);
149149

150150
if (is_lut)
151151
insts.emplace_back(cell_inst, width, init_param);
@@ -157,20 +157,20 @@ struct NetlistReader {
157157
std::string init_param;
158158
std::tie(inst_idx, lut_width, init_param) = inst;
159159

160-
std::string inst_name = str_list[inst_list[inst_idx].getName()].cStr();
160+
std::string inst_name = str_list[inst_list[inst_idx].getName()];
161161

162162
auto props = inst_list[inst_idx].getPropMap().getEntries();
163163
std::vector<bool> init;
164164
for (auto entry : props) {
165-
if (std::string(str_list[entry.getKey()].cStr()) != init_param)
165+
if (str_list[entry.getKey()] != init_param)
166166
continue;
167167

168168
// TODO: export this to a library function to have generic parameter decoding
169169
if (entry.which() == LogicalNetlist::Netlist::PropertyMap::Entry::TEXT_VALUE) {
170170
const std::regex vhex_regex("[0-9]+'h([0-9A-Z]+)");
171171
const std::regex vbit_regex("[0-9]+'b([0-9A-Z]+)");
172172
const std::regex bit_regex("[0-1]+");
173-
std::string init_str = std::string(str_list[entry.getTextValue()].cStr());
173+
std::string init_str = str_list[entry.getTextValue()];
174174
std::smatch regex_matches;
175175

176176
// Fill the init vector
@@ -249,7 +249,7 @@ struct NetlistReader {
249249
std::unordered_map<unsigned int, std::string> port_net_map;
250250

251251
for (auto net : top_cell.getNets()) {
252-
std::string net_name = str_list[net.getName()].cStr();
252+
std::string net_name = str_list[net.getName()];
253253
for (auto port : net.getPortInsts()) {
254254
if (!port.isInst() || port.getInst() != inst_idx)
255255
continue;
@@ -260,6 +260,7 @@ struct NetlistReader {
260260

261261
int inum = 0;
262262
for (auto port : cell_lib.getPorts()) {
263+
if (port_net_map.find(port) == port_net_map.end()) continue;
263264
auto net_name = port_net_map.at(port);
264265
AtomNetId net_id = main_netlist_.create_net(net_name);
265266

@@ -291,7 +292,7 @@ struct NetlistReader {
291292
auto cell = decl_list[inst_list[cell_inst].getCell()];
292293

293294
bool is_lut;
294-
std::tie(is_lut, std::ignore, std::ignore) = is_lut_cell(str_list[cell.getName()].cStr());
295+
std::tie(is_lut, std::ignore, std::ignore) = is_lut_cell(str_list[cell.getName()]);
295296

296297
if (!is_lut)
297298
insts.emplace_back(cell_inst, inst_list[cell_inst].getCell());
@@ -301,10 +302,10 @@ struct NetlistReader {
301302
auto inst_idx = inst_pair.first;
302303
auto cell_idx = inst_pair.second;
303304

304-
auto model_name = str_list[decl_list[cell_idx].getName()].cStr();
305+
auto model_name = str_list[decl_list[cell_idx].getName()];
305306
const t_model* blk_model = find_model(model_name);
306307

307-
std::string inst_name = str_list[inst_list[inst_idx].getName()].cStr();
308+
std::string inst_name = str_list[inst_list[inst_idx].getName()];
308309
VTR_ASSERT(inst_name.empty() == 0);
309310

310311
//The name for every block should be unique, check that there is no name conflict
@@ -320,9 +321,9 @@ struct NetlistReader {
320321
auto port_net_map = get_port_net_map(inst_idx);
321322

322323
auto cell = decl_list[inst_list[inst_idx].getCell()];
323-
if (std::string(str_list[cell.getName()].cStr()) == arch_.vcc_cell)
324+
if (str_list[cell.getName()] == arch_.vcc_cell)
324325
inst_name = arch_.vcc_cell;
325-
else if (std::string(str_list[cell.getName()].cStr()) == arch_.gnd_cell)
326+
else if (str_list[cell.getName()] == arch_.gnd_cell)
326327
inst_name = arch_.gnd_cell;
327328

328329
if (main_netlist_.find_block(inst_name))
@@ -343,7 +344,7 @@ struct NetlistReader {
343344
net_name = arch_.gnd_net;
344345

345346
auto port = port_list[port_idx];
346-
auto port_name = str_list[port.getName()].cStr();
347+
auto port_name = str_list[port.getName()];
347348

348349
//Check for consistency between model and ports
349350
const t_model_ports* model_port = find_model_port(blk_model, std::string(port_name));
@@ -443,7 +444,7 @@ struct NetlistReader {
443444
auto str_list = nr_.getStrList();
444445
std::unordered_map<std::pair<unsigned int, unsigned int>, std::string, vtr::hash_pair> map;
445446
for (auto net : top_cell.getNets()) {
446-
std::string net_name = str_list[net.getName()].cStr();
447+
std::string net_name = str_list[net.getName()];
447448
for (auto port : net.getPortInsts()) {
448449
if (!port.isInst() || port.getInst() != inst_idx)
449450
continue;

‎vpr/src/place/place.cpp

Lines changed: 0 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -237,10 +237,6 @@ std::unique_ptr<FILE, decltype(&vtr::fclose)> f_move_stats_file(nullptr,
237237
#endif
238238

239239
/********************* Static subroutines local to place.c *******************/
240-
#ifdef VERBOSE
241-
static void print_clb_placement(const char* fname);
242-
#endif
243-
244240
static void alloc_and_load_placement_structs(float place_cost_exp,
245241
const t_placer_opts& placer_opts,
246242
t_direct_inf* directs,
@@ -2850,25 +2846,6 @@ int check_macro_placement_consistency() {
28502846
return error;
28512847
}
28522848

2853-
#ifdef VERBOSE
2854-
static void print_clb_placement(const char* fname) {
2855-
/* Prints out the clb placements to a file. */
2856-
FILE* fp;
2857-
auto& cluster_ctx = g_vpr_ctx.clustering();
2858-
auto& place_ctx = g_vpr_ctx.placement();
2859-
2860-
fp = vtr::fopen(fname, "w");
2861-
fprintf(fp, "Complex block placements:\n\n");
2862-
2863-
fprintf(fp, "Block #\tName\t(X, Y, Z).\n");
2864-
for (auto i : cluster_ctx.clb_nlist.blocks()) {
2865-
fprintf(fp, "#%d\t%s\t(%d, %d, %d).\n", i, cluster_ctx.clb_nlist.block_name(i), place_ctx.block_locs[i].x, place_ctx.block_locs[i].y, place_ctx.block_locs[i].sub_tile);
2866-
}
2867-
2868-
fclose(fp);
2869-
}
2870-
#endif
2871-
28722849
static void free_try_swap_arrays() {
28732850
g_vpr_ctx.mutable_placement().compressed_block_grids.clear();
28742851
}

‎vpr/src/place/place_util.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -462,3 +462,22 @@ void set_block_location(ClusterBlockId blk_id, const t_pl_loc& location) {
462462
place_ctx.grid_blocks[location.x][location.y].blocks[location.sub_tile] = blk_id;
463463
place_ctx.grid_blocks[location.x][location.y].usage++;
464464
}
465+
466+
#ifdef VERBOSE
467+
void print_clb_placement(const char* fname) {
468+
/* Prints out the clb placements to a file. */
469+
FILE* fp;
470+
auto& cluster_ctx = g_vpr_ctx.clustering();
471+
auto& place_ctx = g_vpr_ctx.placement();
472+
473+
fp = vtr::fopen(fname, "w");
474+
fprintf(fp, "Complex block placements:\n\n");
475+
476+
fprintf(fp, "Block #\tName\t(X, Y, Z).\n");
477+
for (auto i : cluster_ctx.clb_nlist.blocks()) {
478+
fprintf(fp, "#%d\t%s\t(%d, %d, %d).\n", i, cluster_ctx.clb_nlist.block_name(i).c_str(), place_ctx.block_locs[i].loc.x, place_ctx.block_locs[i].loc.y, place_ctx.block_locs[i].loc.sub_tile);
479+
}
480+
481+
fclose(fp);
482+
}
483+
#endif

‎vpr/src/place/place_util.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,10 @@ class t_placer_statistics {
201201
void single_swap_update(const t_placer_costs& costs);
202202
};
203203

204+
#ifdef VERBOSE
205+
void print_clb_placement(const char* fname);
206+
#endif
207+
204208
///@brief Initialize the placer's block-grid dual direction mapping.
205209
void init_placement_context();
206210

‎vpr/src/place/timing_place_lookup.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -501,7 +501,7 @@ static void generic_compute_matrix_dijkstra_expansion(
501501

502502
#ifdef VERBOSE
503503
VTR_LOG("Computed delay: %12g delta: %d,%d (src: %d,%d sink: %d,%d)\n",
504-
delay,
504+
delays[size_t(sink_rr_node)],
505505
delta_x, delta_y,
506506
source_x, source_y,
507507
sink_x, sink_y);

‎vpr/src/route/rr_graph.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1285,7 +1285,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder,
12851285
if ((i == 0 && side != RIGHT)
12861286
|| (i == int(grid.width() - 1) && side != LEFT)
12871287
|| (j == 0 && side != TOP)
1288-
|| (j == int(grid.width() - 1) && side != BOTTOM)) {
1288+
|| (j == int(grid.height() - 1) && side != BOTTOM)) {
12891289
return;
12901290
}
12911291

0 commit comments

Comments
 (0)