Skip to content

removing assert statements #21

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
May 25, 2021
Merged
Changes from 3 commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
35 changes: 23 additions & 12 deletions adafruit_si5351.py
Original file line number Diff line number Diff line change
Expand Up @@ -169,10 +169,11 @@ def _configure_registers(self, p1, p2, p3):
self._si5351._write_u8(_SI5351_REGISTER_177_PLL_RESET, (1 << 7) | (1 << 5))

def configure_integer(self, multiplier):
"""Configure the PLL with a simple integer mulitplier for the most
"""Configure the PLL with a simple integer multiplier for the most
accurate (but more limited) PLL frequency generation.
"""
assert 14 < multiplier < 91
if multiplier >= 91 or multiplier <= 14:
raise Exception("Multiplier must be in range 14 to 91.")
multiplier = int(multiplier)
# Compute register values and configure them.
p1 = 128 * multiplier - 512
Expand All @@ -192,9 +193,12 @@ def configure_fractional(self, multiplier, numerator, denominator):
multiplier and numerator/denominator. This is less accurate and
susceptible to jitter but allows a larger range of PLL frequencies.
"""
assert 14 < multiplier < 91
assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
assert 0 <= numerator < 0xFFFFF
if multiplier >= 91 or multiplier <= 14:
raise Exception("Multiplier must be in range 14 to 91.")
if denominator > 0xFFFFF or denominator <= 0: # Prevent divide by zero.
raise Exception("Denominator must be in range 0 to 0xFFFFF.")
if numerator >= 0xFFFFF or numerator < 0:
raise Exception("Numerator must be in range 0 to 0xFFFFF.")
multiplier = int(multiplier)
numerator = int(numerator)
denominator = int(denominator)
Expand Down Expand Up @@ -279,7 +283,8 @@ def r_divider(self):

@r_divider.setter
def r_divider(self, divider):
assert 0 <= divider <= 7
if divider > 7 or divider < 0:
raise Exception("Divider must in range 0 to 7.")
reg_value = self._si5351._read_u8(self._r)
reg_value &= 0x0F
divider &= 0x07
Expand All @@ -306,10 +311,12 @@ def configure_integer(self, pll, divider):
divider. This is the most accurate way to set the clock output
frequency but supports less of a range of values.
"""
assert 3 < divider < 2049
if divider >= 2049 or divider <= 3:
raise Exception("Divider must be in range 3 to 2049.")
divider = int(divider)
# Make sure the PLL is configured (has a frequency set).
assert pll.frequency is not None
if pll.frequency is None:
raise Exception("PLL must be configured.")
# Compute MSx register values.
p1 = 128 * divider - 512
p2 = 0
Expand All @@ -331,14 +338,18 @@ def configure_fractional(self, pll, divider, numerator, denominator):
fractional divider with numerator/denominator. Again this is less
accurate but has a wider range of output frequencies.
"""
assert 3 < divider < 2049
assert 0 < denominator <= 0xFFFFF # Prevent divide by zero.
assert 0 <= numerator < 0xFFFFF
if divider >= 2049 or divider <= 3:
raise Exception("Divider must be in range 3 to 2049.")
if denominator > 0xFFFFF or denominator <= 0: # Prevent divide by zero.
raise Exception("Denominator must be in range 0 to 0xFFFFF.")
if numerator >= 0xFFFFF or numerator < 0:
raise Exception("Numerator must be in range 0 to 0xFFFFF.")
divider = int(divider)
numerator = int(numerator)
denominator = int(denominator)
# Make sure the PLL is configured (has a frequency set).
assert pll.frequency is not None
if pll.frequency is None:
raise Exception("PLL must be configured.")
# Compute MSx register values.
p1 = int(128 * divider + math.floor(128 * (numerator / denominator)) - 512)
p2 = int(
Expand Down