ODIN II: update response to hard block name collisions

ODIN_II/SRC/netlist_create_from_ast.cpp

@@ -5832,6 +5832,8 @@ signal_list_t *create_hard_block(ast_node_t* block, char *instance_name_prefix,
 			/* add the net to the list of inputs */
 			sc_spot = sc_add_string(input_nets_sc, pin_name);
 			input_nets_sc->data[sc_spot] = (void*)new_net;
+
+			vtr::free(pin_name);
 		}
 		current_out_idx += j;
 	}
@@ -5890,6 +5892,8 @@ signal_list_t *create_hard_block(ast_node_t* block, char *instance_name_prefix,
 			/* add the net to the list of inputs */
 			sc_spot = sc_add_string(input_nets_sc, pin_name);
 			input_nets_sc->data[sc_spot] = (void*)new_net;
+
+			vtr::free(pin_name);
 		}
 		current_out_idx += j;
 	}

ODIN_II/SRC/parse_making_ast.cpp

@@ -1507,10 +1507,13 @@ ast_node_t *newModule(char* module_name, ast_node_t *list_of_parameters, ast_nod
 	long sc_spot;
 	ast_node_t *symbol_node = newSymbolNode(module_name, line_number);
 
-	if(sc_lookup_string(hard_block_names, module_name) != -1)
+	if( sc_lookup_string(hard_block_names, module_name) != -1
+		|| !strcmp(module_name, SINGLE_PORT_RAM_string)
+		|| !strcmp(module_name, DUAL_PORT_RAM_string)
+	)
 	{
-		warning_message(PARSE_ERROR, line_number, current_parse_file, 
-			"Probable module name collision with hard block of the same name -> %s\n", module_name);		
+		error_message(PARSE_ERROR, line_number, current_parse_file, 
+			"Module name collides with hard block of the same name (%s)\n", module_name);		
 	}
 
 	/* create a node for this array reference */

ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf

@@ -2,6 +2,7 @@ regression_test/benchmark/task/arch_sweep
 regression_test/benchmark/task/rs_decoder
 regression_test/benchmark/task/cmd_line_args/*
 regression_test/benchmark/task/func_simulator/*
+regression_test/benchmark/task/hard_blocks
 regression_test/benchmark/task/multiclock/*
 regression_test/benchmark/task/operators
 regression_test/benchmark/task/syntax

ODIN_II/regression_test/benchmark/task/hard_blocks/task.conf

@@ -0,0 +1,17 @@
+########################
+# hard blocks benchmarks config
+########################
+
+script_synthesis_params=--time_limit 3600s --tool valgrind
+script_simulation_params=--time_limit 3600s
+
+# setup the architecture
+arch_dir=../vtr_flow/arch/timing
+
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# setup the circuits
+circuit_dir=regression_test/benchmark/verilog/micro
+
+circuit_list_add=adder_hard_block.v
+circuit_list_add=multiply_hard_block.v

ODIN_II/regression_test/benchmark/task/micro/task.conf

@@ -80,3 +80,8 @@ circuit_list_add=bm_if_common.v
 circuit_list_add=bm_if_collapse.v
 circuit_list_add=case_generate.v
 circuit_list_add=if_generate.v
+
+# these require specific architectures to run without errors
+
+# circuit_list_add=adder_hard_block.v
+# circuit_list_add=multiply_hard_block.v

ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block.v

@@ -0,0 +1,13 @@
+module top_module
+(
+
+    input [1:0] a1, b1, a2, b2,
+    input cin1, cin2,
+    output [1:0] sumout1, sumout2,
+    output cout1, cout2
+);
+
+    adder a1 (.a(a1), .b(b1), .cin(cin1), .sumout(sumout1), .cout(cout1));
+    adder a2 (a2, b2, cin2, sumout2, cout2);
+
+endmodule

ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_input

@@ -0,0 +1,101 @@
+GLOBAL_SIM_BASE_CLK a1 b1 a2 b2 cin1 cin2
+1 0X2 0X3 0X1 0X2 1 0 
+0 0X2 0X1 0X0 0X0 1 0 
+1 0X1 0X0 0X3 0X3 0 0 
+0 0X3 0X1 0X1 0X3 1 1 
+1 0X1 0X2 0X2 0X2 0 0 
+0 0X0 0X2 0X3 0X2 0 1 
+1 0X3 0X1 0X1 0X1 1 0 
+0 0X1 0X1 0X0 0X0 1 1 
+1 0X1 0X0 0X2 0X0 0 0 
+0 0X1 0X0 0X3 0X1 1 0 
+1 0X2 0X0 0X3 0X1 1 0 
+0 0X3 0X3 0X3 0X3 1 0 
+1 0X1 0X1 0X3 0X0 1 0 
+0 0X3 0X0 0X2 0X2 0 1 
+1 0X1 0X3 0X3 0X0 0 1 
+0 0X1 0X0 0X0 0X1 1 1 
+1 0X3 0X0 0X3 0X2 1 0 
+0 0X2 0X3 0X3 0X0 1 1 
+1 0X1 0X2 0X3 0X0 0 0 
+0 0X0 0X3 0X1 0X2 0 1 
+1 0X1 0X1 0X2 0X1 0 1 
+0 0X0 0X3 0X1 0X2 0 0 
+1 0X1 0X0 0X2 0X2 1 1 
+0 0X2 0X0 0X0 0X2 0 0 
+1 0X0 0X1 0X0 0X0 1 1 
+0 0X2 0X3 0X1 0X1 0 1 
+1 0X3 0X2 0X3 0X0 1 0 
+0 0X0 0X0 0X0 0X2 1 0 
+1 0X2 0X0 0X2 0X1 0 0 
+0 0X2 0X1 0X3 0X3 1 0 
+1 0X1 0X3 0X2 0X0 0 0 
+0 0X2 0X2 0X0 0X0 0 0 
+1 0X1 0X1 0X0 0X1 0 0 
+0 0X3 0X1 0X2 0X0 1 1 
+1 0X0 0X1 0X2 0X2 1 1 
+0 0X2 0X1 0X2 0X0 0 0 
+1 0X1 0X0 0X1 0X0 0 0 
+0 0X1 0X3 0X1 0X0 1 0 
+1 0X1 0X0 0X3 0X2 1 1 
+0 0X1 0X2 0X0 0X1 1 1 
+1 0X0 0X1 0X0 0X1 0 0 
+0 0X2 0X3 0X1 0X2 0 1 
+1 0X2 0X3 0X2 0X2 1 0 
+0 0X1 0X3 0X3 0X1 0 1 
+1 0X3 0X0 0X3 0X2 0 0 
+0 0X3 0X0 0X1 0X2 1 1 
+1 0X1 0X1 0X3 0X0 0 0 
+0 0X0 0X1 0X0 0X0 0 0 
+1 0X0 0X1 0X2 0X2 0 1 
+0 0X3 0X0 0X2 0X0 0 1 
+1 0X3 0X2 0X1 0X3 0 0 
+0 0X0 0X2 0X0 0X3 1 1 
+1 0X2 0X3 0X2 0X3 1 1 
+0 0X1 0X3 0X2 0X0 1 0 
+1 0X3 0X3 0X0 0X3 1 1 
+0 0X0 0X3 0X1 0X0 0 1 
+1 0X3 0X1 0X3 0X3 1 1 
+0 0X0 0X2 0X1 0X0 1 1 
+1 0X0 0X0 0X1 0X0 1 1 
+0 0X0 0X2 0X3 0X1 1 1 
+1 0X0 0X0 0X3 0X1 1 1 
+0 0X3 0X1 0X1 0X1 1 0 
+1 0X2 0X2 0X0 0X1 1 1 
+0 0X2 0X3 0X2 0X2 0 0 
+1 0X1 0X3 0X3 0X3 0 1 
+0 0X0 0X1 0X3 0X0 0 0 
+1 0X3 0X3 0X1 0X3 0 0 
+0 0X1 0X3 0X1 0X1 1 1 
+1 0X3 0X0 0X1 0X2 0 0 
+0 0X3 0X0 0X2 0X0 1 0 
+1 0X2 0X1 0X2 0X2 0 1 
+0 0X2 0X0 0X2 0X0 0 0 
+1 0X0 0X3 0X2 0X0 0 0 
+0 0X3 0X3 0X1 0X1 1 1 
+1 0X3 0X1 0X2 0X0 0 0 
+0 0X1 0X2 0X2 0X3 0 0 
+1 0X2 0X1 0X2 0X3 0 0 
+0 0X2 0X3 0X3 0X0 1 1 
+1 0X1 0X0 0X3 0X1 1 1 
+0 0X2 0X2 0X3 0X2 0 0 
+1 0X3 0X0 0X1 0X3 0 1 
+0 0X2 0X1 0X2 0X3 0 0 
+1 0X2 0X0 0X3 0X2 0 0 
+0 0X0 0X0 0X2 0X2 1 0 
+1 0X0 0X3 0X0 0X1 1 0 
+0 0X1 0X3 0X0 0X1 1 1 
+1 0X2 0X3 0X1 0X2 0 0 
+0 0X3 0X0 0X1 0X3 1 1 
+1 0X0 0X3 0X1 0X0 1 0 
+0 0X0 0X0 0X2 0X2 1 0 
+1 0X1 0X3 0X1 0X1 1 1 
+0 0X1 0X3 0X3 0X2 0 0 
+1 0X0 0X0 0X2 0X1 1 1 
+0 0X1 0X2 0X1 0X3 1 0 
+1 0X2 0X0 0X1 0X2 1 1 
+0 0X3 0X1 0X0 0X2 0 1 
+1 0X0 0X3 0X1 0X2 0 0 
+0 0X0 0X1 0X1 0X0 1 1 
+1 0X1 0X3 0X2 0X3 1 0 
+0 0X2 0X3 0X1 0X3 1 1 

ODIN_II/regression_test/benchmark/verilog/micro/adder_hard_block_output

@@ -0,0 +1,101 @@
+sumout1 sumout2 cout1 cout2
+0X1 0X3 1 0 
+0X3 0X0 0 0 
+0X1 0X2 0 1 
+0X0 0X0 1 1 
+0X3 0X0 0 1 
+0X2 0X1 0 1 
+0X0 0X2 1 0 
+0X2 0X0 0 0 
+0X1 0X2 0 0 
+0X1 0X0 0 1 
+0X2 0X0 0 1 
+0X2 0X2 1 1 
+0X2 0X3 0 0 
+0X3 0X0 0 1 
+0X0 0X3 1 0 
+0X1 0X1 0 0 
+0X3 0X1 0 1 
+0X1 0X3 1 0 
+0X3 0X3 0 0 
+0X3 0X3 0 0 
+0X2 0X3 0 0 
+0X3 0X3 0 0 
+0X1 0X0 0 1 
+0X2 0X2 0 0 
+0X1 0X0 0 0 
+0X1 0X2 1 0 
+0X1 0X3 1 0 
+0X0 0X2 0 0 
+0X2 0X3 0 0 
+0X3 0X2 0 1 
+0X0 0X2 1 0 
+0X0 0X0 1 0 
+0X2 0X1 0 0 
+0X0 0X2 1 0 
+0X1 0X0 0 1 
+0X3 0X2 0 0 
+0X1 0X1 0 0 
+0X0 0X1 1 0 
+0X1 0X1 0 1 
+0X3 0X1 0 0 
+0X1 0X1 0 0 
+0X1 0X3 1 0 
+0X1 0X0 1 1 
+0X0 0X0 1 1 
+0X3 0X1 0 1 
+0X3 0X3 0 0 
+0X2 0X3 0 0 
+0X1 0X0 0 0 
+0X1 0X0 0 1 
+0X3 0X2 0 0 
+0X1 0X0 1 1 
+0X2 0X3 0 0 
+0X1 0X1 1 1 
+0X0 0X2 1 0 
+0X2 0X3 1 0 
+0X3 0X1 0 0 
+0X0 0X2 1 1 
+0X2 0X1 0 0 
+0X0 0X1 0 0 
+0X2 0X0 0 1 
+0X0 0X0 0 1 
+0X0 0X2 1 0 
+0X0 0X1 1 0 
+0X1 0X0 1 1 
+0X0 0X2 1 1 
+0X1 0X3 0 0 
+0X2 0X0 1 1 
+0X0 0X2 1 0 
+0X3 0X3 0 0 
+0X3 0X2 0 0 
+0X3 0X0 0 1 
+0X2 0X2 0 0 
+0X3 0X2 0 0 
+0X2 0X2 1 0 
+0X0 0X2 1 0 
+0X3 0X1 0 1 
+0X3 0X1 0 1 
+0X1 0X3 1 0 
+0X1 0X0 0 1 
+0X0 0X1 1 1 
+0X3 0X0 0 1 
+0X3 0X1 0 1 
+0X2 0X1 0 1 
+0X0 0X0 0 1 
+0X3 0X1 0 0 
+0X0 0X1 1 0 
+0X1 0X3 1 0 
+0X3 0X0 0 1 
+0X3 0X1 0 0 
+0X0 0X0 0 1 
+0X0 0X2 1 0 
+0X0 0X1 1 1 
+0X0 0X3 0 0 
+0X3 0X0 0 1 
+0X2 0X3 0 0 
+0X0 0X2 1 0 
+0X3 0X3 0 0 
+0X1 0X1 0 0 
+0X0 0X1 1 1 
+0X1 0X0 1 1 

ODIN_II/regression_test/benchmark/verilog/micro/multiply_hard_block.v

@@ -0,0 +1,11 @@
+module top_module
+(
+
+    input [1:0] x1, x2, x3, x4,
+    output [3:0] y1, y2
+);
+
+    multiply m1 (.a(x1), .b(x2), .out(y1));
+    multiply m2 (x3, x4, y2);
+
+endmodule