Add tileable RR Graph #3134

amin1377 · 2025-06-11T18:14:24Z

Merging OpenFPGA branch into master branch. PR #2135 explains features of OpenFPGA.

…le info

…rilog-to-routing into add_tileable_rr_graph

amin1377 · 2025-06-19T22:35:52Z

Hi @AlexandreSinger,

I think the PR is ready for your first round of review. I'd appreciate it if you could take a look. Thanks!

amin1377 · 2025-06-19T22:37:00Z

Hi @soheilshahrouz,

This PR is ready for your review. Since you're familiar with the RR Graph code, it would be great if you could take a look at the tileable RR Graph implementation.

…rilog-to-routing into add_tileable_rr_graph

AlexandreSinger

Hi @amin1377 thanks for bringing this in! I recognize not all of this is your code. Overall the code is well structured however it needs some code style and data structure cleanup so it can fit in better with the rest of the VTR flow.

Some. of the data structure changes can be made into issues; however, the coding style things should probably be fixed now.

AlexandreSinger · 2025-06-19T22:39:22Z

doc/src/arch/reference.rst

+
+  Technical details can be found in :cite:`XTang_FPT_2019`. 
+
+  .. note:: Strongly recommend to enable the tileable routing architecture when you want to PnR large FPGA fabrics, which can effectively reduce the runtime.


Strongly recommend -> It is strongly recommended to

AlexandreSinger · 2025-06-19T22:40:05Z

doc/src/arch/reference.rst

+
+.. option:: through_channel="<bool>"
+
+  Allow routing channels to pass through multi-width and multi-height programable blocks. This is mainly used in heterogeneous FPGAs to increase routability, as illustrated in :numref:`fig_thru_channel`.


programable -> programmable

AlexandreSinger · 2025-06-19T22:42:12Z

doc/src/arch/reference.rst

+
+.. note:: These options are required
+
+In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection:


Are we destinguishing OpenFPGA architecture files from regular architecture files?

AlexandreSinger · 2025-06-19T22:43:12Z

doc/src/arch/reference.rst

+    <direct name="scff_chain" from_pin="clb.sc_out" to_pin="clb.sc_in" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+
+In OpenFPGA architecture:


Same comment as above. Is our goal to maintain a separate architecture description file for OpenFPGA and VPR?

I would prefer if we could limit this as much as possible such that an "OpenFPGA" architecture and VPR architecture are one in the same.

AlexandreSinger · 2025-06-19T22:46:05Z

doc/src/vpr/VIB.rst

@@ -0,0 +1,254 @@
+.. _VIB:
+
+VIB Architecture


What does VIB. I think this file also needs some context. Why is it here? Who should be using this architecture?

AlexandreSinger · 2025-06-20T03:05:40Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

+            default:
+                VTR_LOGF_ERROR(__FILE__, __LINE__,
+                               "Invalid side index!\n");
+                exit(1);


exit(1) should not be used here.

AlexandreSinger · 2025-06-20T03:06:35Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

+            default:
+                VTR_LOGF_ERROR(__FILE__, __LINE__,
+                               "Invalid side index!\n");
+                exit(1);


exit(1) should not be used here.

AlexandreSinger · 2025-06-20T03:08:14Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp

+                if (from.type_name != vib->get_pbtype_name()) {
+                    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                                   "Wrong from type name!\n");
+                    exit(1);


Another exit(1) here and just below.

There are actually a lot in this function.

AlexandreSinger · 2025-06-20T03:10:25Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.h

@@ -0,0 +1,57 @@
+#ifndef TILEABLE_RR_GRAPH_NODE_BUILDER_H


Pragma once + file comment.

AlexandreSinger · 2025-06-20T03:11:51Z

vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp

+                default:
+                    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                                   "Invalid routing resource node!\n");
+                    exit(1);


exit(1) here and throughout this file.

amin1377 added 19 commits June 11, 2025 09:55

[vpr][rr_graph] add tileable rr graph dir

b6371d2

[vpr][rr_graph] move tileable rr graph dir uner rr_graph_generation

77781b4

[vpr][route] update rr_graph generation with tileable rr graph

cf95e2c

[vpr][util] add is_inter_cluster_node for vib arch

431923c

[vpr][route] update router lookahead with tileable rr graph

d62fb79

[vpr][blif] use regex to find param val

02a56e9

[vpr][base] update with tileable rr graph

204a794

[vpr][route] remove unused param

7edf56d

[lib][arch] add vib processing

f5e8061

[lib][arch] add vib_inf

14064c7

[libs][rr_graph] update lib rr graph with tileable

49b04b0

[libs][rr graph][io] update read/write rr graph functions with tileab…

c6df91a

…le info

[libs][rr graph][io] update rr_grpah utils with tileable info

bf19150

[lib][rr_graph] add vtr tokenizer

3970db7

[lib][util] update capnp and util with open fpga

797b488

add openfpga doc

cf2dbc8

[vpr][base] add vib grid

0e03dc7

add VIB doc

f8fae78

[vpr][route] fix alloc_and_load_rr_switch_inf definition

5462ccd

github-actions bot added VPR VPR FPGA Placement & Routing Tool libarchfpga Library for handling FPGA Architecture descriptions docs Documentation lang-cpp C/C++ code libvtrutil labels Jun 11, 2025

amin1377 added 6 commits June 11, 2025 14:15

make format

7cdf5bf

[vtr_flow][test] add openfpga arch

5ad8303

[CI] add openfpga tests

c79ab8f

fix formatting

8eccbcc

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

0cc6f10

…rilog-to-routing into add_tileable_rr_graph

[doc][arch] add tileable doc

5a492c8

amin1377 added 20 commits June 16, 2025 08:33

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

1fd866e

…rilog-to-routing into add_tileable_rr_graph

[libs][arch] add function declarations

5580c86

[rr_graph] change MEDIUM node type name and related function to MUX

a27f6ba

[libs][arch] add process_bend

8625ff0

make format

57c1919

[doc] fix a typo in .bib file

29c9677

[vpr] remove redundant version of is_inter_cluster_node

b6fdda3

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

2b68252

…rilog-to-routing into add_tileable_rr_graph

[doc][arch] move openfpga doc to the end of the file

65102b9

[doc][arch] add figures related to direct connection

757e2f7

[doc][arch] add doc related to tileable direct interconnect

2b2fbb4

[arch] change isbend to is_bend

6e5070c

[tileable_rr_graph] fix sub_fs formatting

43ac8b4

[rr_graph] comment tileable rr_graph function under rr_graph_builder.h

5436025

[libs][rr_graph] mode bend_start/end out of t_rr_node_data

09c90f2

[base] fix function names formatting

e3df5b5

make format

e08cd8c

[libs][matrix] check for size before filling the matrix

9c87418

[libs][rr_graph] fix node_bend_start/end size

0df7730

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

837278b

…rilog-to-routing into add_tileable_rr_graph

amin1377 requested a review from AlexandreSinger June 19, 2025 22:36

amin1377 requested a review from soheilshahrouz June 19, 2025 22:37

Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…

7c6a979

…rilog-to-routing into add_tileable_rr_graph

AlexandreSinger requested changes Jun 20, 2025

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Add tileable RR Graph #3134

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amin1377 commented Jun 11, 2025 •

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		Technical details can be found in :cite:`XTang_FPT_2019`.

		.. note:: Strongly recommend to enable the tileable routing architecture when you want to PnR large FPGA fabrics, which can effectively reduce the runtime.


		.. option:: through_channel="<bool>"

		Allow routing channels to pass through multi-width and multi-height programable blocks. This is mainly used in heterogeneous FPGAs to increase routability, as illustrated in :numref:`fig_thru_channel`.


		.. note:: These options are required

		In the OpenFPGA architecture file, you may define additional attributes for each VPR's direct connection:

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amin1377 commented Jun 11, 2025 •

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