[STA] Updated Tutorial

doc/src/tutorials/timing_analysis/index.rst

@@ -6,6 +6,8 @@ Post-Implementation Timing Analysis
 This tutorial describes how to perform static timing analysis (STA) on a circuit which has
 been implemented by :ref:`VPR` using OpenSTA, an external timing analysis tool.
 
+A video of this tutorial can be found here: https://youtu.be/yihFJc7WOfE
+
 External timing analysis can be useful since VPR's timing analyzer (Tatum) does
 not support all timing constraints and does not provide a TCL interface to allow
 you to directly interrogate the timing graph. VPR also has limited support for

vpr/src/base/netlist_writer.cpp

@@ -2716,8 +2716,8 @@ void add_propagated_clocks_to_sdc_file(std::ofstream& sdc_os) {
     sdc_os << "#******************************************************************************#\n";
     sdc_os << "# The following are clock domains in VPR which have delays on their edges.\n";
     sdc_os << "#\n";
-    sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a";
-    sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this";
+    sdc_os << "# Any non-virtual clock has its delay determined and written out as part of a\n";
+    sdc_os << "# propagated clock command. If VPR was instructed not to route the clock, this\n";
     sdc_os << "# delay will be an underestimate.\n";
     sdc_os << "#\n";
     sdc_os << "# Note: Virtual clocks do not get routed and are treated as ideal.\n";