Skip to content

[FGParallelRouter] Updated Barrier to C++20 Std Barrier #3052

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Conversation

AlexandreSinger
Copy link
Contributor

The fine-grained parallel router was originally built before VTR upgraded to C++20, so we had to roll our own barrier. We originally had two barriers: spin barriers (thread spin on a lock while waiting) and a "mutex" barrer (where threads wait on a condition variable and potentially went to sleep).

Through experimentation, found that the choice of barrier implementation did not matter; however, the standard barrier provides slight performance improvements for very long routes and has a much cleaner interface.

Moved the FG parallel router to the standard barrier. The old implementations are left in as classes in case c++20 is not preferred for some users.

Also added a QoR script to make parsing FG parallel router runs easier.

The fine-grained parallel router was originally built before VTR
upgraded to C++20, so we had to roll our own barrier. We originally had
two barriers: spin barriers (thread spin on a lock while waiting) and a
"mutex" barrer (where threads wait on a condition variable and
potentially went to sleep).

Through experimentation, found that the choice of barrier implementation
did not matter; however, the standard barrier provides slight
performance improvements for very long routes and has a much cleaner
interface.

Moved the FG parallel router to the standard barrier. The old
implementations are left in as classes in case c++20 is not preferred
for some users.

Also added a QoR script to make parsing FG parallel router runs easier.
@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels May 17, 2025
@AlexandreSinger
Copy link
Contributor Author

AlexandreSinger commented May 17, 2025

Results on the 8 largest VTR circuits using A* algorithm on 4 threads:

circuit Spin Barrier Path Search Time "Mutex" Barrier Path Search Time STD Barrier Path Search Time
arm_core.v 1 1.103752132 1.014496873
bgm.v 1 1.366792878 1.134778055
stereovision0.v 1 1.408060453 1.14861461
stereovision1.v 1 1.079357581 1.037316958
stereovision2.v 1 0.9452167042 0.9310233824
LU8PEEng.v 1 1.160383944 1.053519488
LU32PEEng.v 1 1.031173433 0.998935741
mcml.v 1 1.012473272 0.9592872416
GEOMEAN 1 1.128239139 1.032267145

Raw numbers:

circuit Spin Barrier Path Search Time "Mutex" Barrier Path Search Time STD Barrier Path Search Time
arm_core.v 10.554 11.649 10.707
bgm.v 12.413 16.966 14.086
stereovision0.v 0.794 1.118 0.912
stereovision1.v 6.351 6.855 6.588
stereovision2.v 34.171 32.299 31.814
LU8PEEng.v 17.19 19.947 18.11
LU32PEEng.v 171.011 176.342 170.829
mcml.v 70.15 71.025 67.294

The important thing to notice is that the standard barrier implementation appear to do better on the circuits that spend more time routing, which is the case we care about.

After seeing these results, I chose to make the STD barrier implementation the default.

Raw data: https://docs.google.com/spreadsheets/d/1L5j7zt9wY5EJo7qJHvWhd7r4rnrgiCfiTb9MM0ADeFc/edit?usp=sharing

@AlexandreSinger AlexandreSinger requested a review from ueqri May 17, 2025 18:02
@AlexandreSinger
Copy link
Contributor Author

@vaughnbetz FYI

@AlexandreSinger
Copy link
Contributor Author

@ueqri This PR includes the changes I proposed a few months ago to move us from spin barriers to "mutex" barriers. Since we upgraded to C++20, I also tested the standard barrier and found that it out-performed both of our implementations on larger routing problems (while also being much cleaner). This PR changes the barrier implementation to use the standard barrier.

Please review when you have a moment.

Copy link
Contributor

@vaughnbetz vaughnbetz left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM. I suggest also comparing its runtime to the spin barrier on Titan so we can see if there's a difference there.

Copy link
Contributor

@ueqri ueqri left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Changes look perfect! Thank you for updating this, Alex!

@AlexandreSinger
Copy link
Contributor Author

I ran the spin barrier vs the standard barrier on titan and found the geomean route time to be practically the same.
I had to run the router in directed mode since I was running on Wintermute which was a bit loaded. I wanted to keep the runs short to prevent the load from messing with the results too much.

The standard barrier appears to be slightly faster, but there are some outlier circuits (which I think are from machine load).

Directed 12T results on Titan:

  total_connection_pathsearch_time
LU230_stratixiv_arch_timing.blif 0.9799679814
LU_Network_stratixiv_arch_timing.blif 0.9522263837
SLAM_spheric_stratixiv_arch_timing.blif 1.363800844
bitcoin_miner_stratixiv_arch_timing.blif 0.7219567715
bitonic_mesh_stratixiv_arch_timing.blif 1.395895824
cholesky_bdti_stratixiv_arch_timing.blif 1.165343988
cholesky_mc_stratixiv_arch_timing.blif 1.051733111
dart_stratixiv_arch_timing.blif 1.022826778
denoise_stratixiv_arch_timing.blif 1.755343844
des90_stratixiv_arch_timing.blif 1.019120648
directrf_stratixiv_arch_timing.blif 1.314550076
gsm_switch_stratixiv_arch_timing.blif 1.056555742
mes_noc_stratixiv_arch_timing.blif 0.9716763181
minres_stratixiv_arch_timing.blif 1.002101325
neuron_stratixiv_arch_timing.blif 0.9672196796
openCV_stratixiv_arch_timing.blif 1.295715341
segmentation_stratixiv_arch_timing.blif 0.9722478239
sparcT1_chip2_stratixiv_arch_timing.blif 0.9820244812
sparcT1_core_stratixiv_arch_timing.blif 1.032184341
sparcT2_core_stratixiv_arch_timing.blif 1.130056772
stap_qrd_stratixiv_arch_timing.blif 0.6199612247
stereo_vision_stratixiv_arch_timing.blif 0.609602633
  1.033207115

@AlexandreSinger AlexandreSinger merged commit 0391d48 into verilog-to-routing:master May 20, 2025
66 of 67 checks passed
@AlexandreSinger AlexandreSinger deleted the feature-fg-parallel-mutex-barrier branch May 20, 2025 21:44
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
lang-cpp C/C++ code VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants