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[LibArchFPGA] Updating Model Data Structures #3004

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Merged
merged 1 commit into from
Apr 30, 2025
Merged

[LibArchFPGA] Updating Model Data Structures #3004

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95 changes: 43 additions & 52 deletions libs/libarchfpga/src/arch_check.cpp
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6 changes: 3 additions & 3 deletions libs/libarchfpga/src/arch_check.h
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ extern "C" {
* @param file architecture file
* @param line line in the architecture file that generates the failure
*/
bool check_model_clocks(t_model* model, const char* file, uint32_t line);
bool check_model_clocks(const t_model& model, const char* file, uint32_t line);

/**
* @brief Checks the correctness of the combinational sinks in the model inputs to outputs connections
Expand All @@ -35,7 +35,7 @@ bool check_model_clocks(t_model* model, const char* file, uint32_t line);
* @param file architecture file
* @param line line in the architecture file that generates the failure
*/
bool check_model_combinational_sinks(const t_model* model, const char* file, uint32_t line);
bool check_model_combinational_sinks(const t_model& model, const char* file, uint32_t line);

/**
* @brief Checks whether the I/O ports can have timing specifications based on their connectivity.
Expand All @@ -47,7 +47,7 @@ bool check_model_combinational_sinks(const t_model* model, const char* file, uin
* @param file architecture file
* @param line line in the architecture file that generates the failure
*/
void warn_model_missing_timing(const t_model* model, const char* file, uint32_t line);
void warn_model_missing_timing(const t_model& model, const char* file, uint32_t line);

/**
* @brief Checks the consistency of the mappings between a logical block and the corresponding physical tile.
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9 changes: 0 additions & 9 deletions libs/libarchfpga/src/arch_types.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,18 +18,9 @@
/* Value for UNDEFINED data */
constexpr int UNDEFINED = -1;

/** The total number of predefined blif models */
constexpr int NUM_MODELS_IN_LIBRARY = 4;

/* Maximum value for minimum channel width to avoid overflows of short data type. */
constexpr int MAX_CHANNEL_WIDTH = 8000;

/* Built-in library models */
constexpr const char* MODEL_NAMES = ".names";
constexpr const char* MODEL_LATCH = ".latch";
constexpr const char* MODEL_INPUT = ".input";
constexpr const char* MODEL_OUTPUT = ".output";

enum class e_arch_format {
VTR, ///<VTR-specific device XML format
FPGAInterchange ///<FPGA Interchange device format
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