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Merged
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Apr 26, 2025
Merged

3D Strong Test #3003

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4 changes: 0 additions & 4 deletions ...tr_reg_strong/strong_3d/config/config.txt → ..._strong/strong_3d/3d_cb/config/config.txt
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Expand Up @@ -16,7 +16,6 @@ archs_dir=arch/multi_die/stratixiv_3d
circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif

# Add architectures to list to sweep
arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml
arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml

# Parse info and how to parse
Expand All @@ -29,7 +28,4 @@ qor_parse_file=qor_vpr_titan.txt
pass_requirements_file=pass_requirements_vpr_titan.txt

script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map
script_params_list_add = --place_bounding_box_mode auto_bb
script_params_list_add = --place_bounding_box_mode cube_bb
script_params_list_add = --place_bounding_box_mode per_layer_bb

2 changes: 2 additions & 0 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_cb/config/golden_results.txt
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
3d_full_OPIN_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 48.72 vpr 1.18 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1240720 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1075.1 MiB 12.14 186170 63157 219808 34278 166444 19086 1191.3 MiB 7.46 0.11 5.41016 4.9834 -5385.92 -3.9834 3.13071 0.02 0.0246574 0.0210761 1.78411 1.4367 73601 5.91791 18330 1.47383 25639 35167 11163573 1688400 0 0 2.60031e+07 21349.0 15 354380 4692432 -1 5.20923 2.79354 -5293.11 -4.20923 0 0 7.54 -1 -1 1191.3 MiB 4.03 3.22991 2.72734 1191.3 MiB -1 1.82
31 changes: 31 additions & 0 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/config.txt
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#
############################################
# Configuration file for running experiments
##############################################

# Path to directory of circuits to use
circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv

# Path to directory of SDC files to use
sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv

# Path to directory of architectures to use
archs_dir=arch/multi_die/stratixiv_3d

# Add circuits to list to sweep
circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif

# Add architectures to list to sweep
arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml

# Parse info and how to parse
parse_file=vpr_titan.txt

# How to parse QoR info
qor_parse_file=qor_vpr_titan.txt

# Pass requirements
pass_requirements_file=pass_requirements_vpr_titan.txt

script_params=-starting_stage vpr -track_memory_usage --route_chan_width 300 --max_router_iterations 400 --router_lookahead map

2 changes: 2 additions & 0 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/3d_sb/config/golden_results.txt
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arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time
3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 73.49 vpr 1.36 GiB 42 758 0 0 0 0 success v8.0.0-12506-gd5dc5f7b8 release IPO VTR_ASSERT_LEVEL=2 GNU 11.5.0 on Linux-5.4.0-171-generic x86_64 2025-04-26T07:14:03 qlsof01.quicklogic.com /home/amohaghegh/vtr-verilog-to-routing/vtr_flow/tasks 1423216 13 29 26295 20086 1 12439 800 29 21 1218 LAB auto 1074.8 MiB 12.24 180137 58272 230944 40790 173771 16383 1389.9 MiB 7.97 0.12 5.04678 4.86539 -4206.86 -3.86539 2.46284 0.05 0.02551 0.0218529 1.92289 1.55523 99517 8.00169 32308 2.59773 27919 38196 46358210 11164094 0 0 2.54084e+07 20860.8 14 2001132 6214436 -1 4.98283 2.70637 -5461.41 -3.98283 0 0 9.53 -1 -1 1389.9 MiB 9.59 3.30445 2.79009 1389.9 MiB -1 17.61
7 changes: 0 additions & 7 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_3d/config/golden_results.txt
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3 changes: 2 additions & 1 deletion vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt
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Expand Up @@ -102,4 +102,5 @@ regression_tests/vtr_reg_strong/strong_timing_no_fail
regression_tests/vtr_reg_strong/strong_noc
regression_tests/vtr_reg_strong/strong_flat_router
regression_tests/vtr_reg_strong/strong_routing_constraints
regression_tests/vtr_reg_strong/strong_3d
regression_tests/vtr_reg_strong/strong_3d/3d_cb
regression_tests/vtr_reg_strong/strong_3d/3d_sb