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Merged
merged 569 commits into from
Apr 24, 2025
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4f648f2
[vpr][ap] remove redundant print_pb
amin1377 Mar 18, 2025
e2ac829
Fix styling regressions
AmirhosseinPoolad Mar 19, 2025
9e0d48a
Add reset_bimap helper method to AtomPBBimap
AmirhosseinPoolad Mar 19, 2025
4c61867
Remove copying empty bimap from global context to cluster legalizer
AmirhosseinPoolad Mar 19, 2025
624f251
Refactor is_atom_blk_in_pb function to get two t_pb* arguments
AmirhosseinPoolad Mar 19, 2025
0e6f62a
Merge branch 'master' into refactor_atom_pb_from_packing
AmirhosseinPoolad Mar 19, 2025
dfb6462
Fix minor styling issues
AmirhosseinPoolad Mar 19, 2025
5f7b793
[vpr][pack] reomve redundant function calls
amin1377 Mar 19, 2025
7110636
[vpr][place] fix estimated_wl var name
amin1377 Mar 19, 2025
a6cb33d
[APPack] Updated How APPack Adheres to Given Placement
AlexandreSinger Mar 14, 2025
3a19e8d
Merge pull request #2939 from verilog-to-routing/redundant_print_pb
AlexandreSinger Mar 19, 2025
47fca21
Merge branch 'master' into feature-appack
AlexandreSinger Mar 19, 2025
ab25381
Merge pull request #2934 from AlexandreSinger/feature-appack
AlexandreSinger Mar 19, 2025
04bb518
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Mar 19, 2025
0b526ab
make format
amin1377 Mar 19, 2025
4fdd98d
[vpr][route] remove redundant functions from rr_graph2
amin1377 Mar 19, 2025
4992203
make format
amin1377 Mar 19, 2025
11c9a57
[vpr][route] remove redundant functions from rr_graph2
amin1377 Mar 19, 2025
1a17be2
[libs][rr_graph] change rr_node_indices value type to RRNodeId
amin1377 Mar 19, 2025
9338a57
fix formatting issues
amin1377 Mar 19, 2025
c115a4a
make format
amin1377 Mar 19, 2025
0af49af
Merge pull request #2938 from verilog-to-routing/init_place_wl
amin1377 Mar 19, 2025
c6802d6
Merge pull request #2941 from verilog-to-routing/rr_node_indices
vaughnbetz Mar 20, 2025
f77c3c7
Merge branch 'master' into refactor_atom_pb_from_packing
AmirhosseinPoolad Mar 20, 2025
ccb2396
Merge pull request #2932 from AmirhosseinPoolad/refactor_atom_pb_from…
AmirhosseinPoolad Mar 20, 2025
ce50295
[AP][GlobalPlacement] Improved Partial Legalizer Legality
AlexandreSinger Mar 19, 2025
c9e6075
Merge pull request #2942 from AlexandreSinger/feature-ap-partial-lega…
AlexandreSinger Mar 20, 2025
e824925
[vpr][rr_graph] fix comment
amin1377 Mar 20, 2025
b26c2d2
[AP][Solver] Supporting Unfixed Blocks
AlexandreSinger Mar 20, 2025
b3d9694
Merge pull request #2944 from AlexandreSinger/feature-ap-solver
amin1377 Mar 21, 2025
0fcbf83
[vpr] rename arch_opin_between_dice_switch to arch_inter_die_switch s…
amin1377 Mar 21, 2025
22d1d72
[arch] fix 3d sb arch delay
amin1377 Mar 21, 2025
0d66f45
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Mar 21, 2025
24f751f
[arch] add ipin_cblock switch
amin1377 Mar 21, 2025
2816b6e
make format
amin1377 Mar 21, 2025
0c27255
Update clang-format version to 18
AmirhosseinPoolad Mar 20, 2025
1cecbab
Fix formatting to be compliant with clang-format-18
AmirhosseinPoolad Mar 21, 2025
674cad5
Merge branch 'master' into fix_clang_format_version
AmirhosseinPoolad Mar 21, 2025
ef52ece
[APPack] Flat-Placement Informed Unrelated Clustering
AlexandreSinger Mar 20, 2025
e7f3a02
Merge pull request #2945 from verilog-to-routing/fix_clang_format_ver…
AlexandreSinger Mar 22, 2025
9c87044
Merge branch 'master' into feature-appack
AlexandreSinger Mar 22, 2025
53b0cad
Merge pull request #2947 from AlexandreSinger/feature-appack
AlexandreSinger Mar 22, 2025
e3f8e13
apply comments
amin1377 Mar 23, 2025
8d6ce93
make format
amin1377 Mar 23, 2025
648413c
[vpr][rr_graph] remove flat router parameter from vpr_create_device
amin1377 Mar 24, 2025
df0d366
[vpr][stats] add print_resource_usage
amin1377 Mar 24, 2025
6827824
[vpr][base] moove calculate_device_util to stats
amin1377 Mar 24, 2025
283343d
[vpr][pack] include required lib
amin1377 Mar 24, 2025
ef74c24
add print_device_util to stats
amin1377 Mar 24, 2025
7a860a2
[vpr][base] print resource usage and device util only if clb netlist …
amin1377 Mar 24, 2025
5bd8624
[vpr][base] remove unused param
amin1377 Mar 24, 2025
7bf5c1f
[vpr][base] remove var from doxygen comment
amin1377 Mar 24, 2025
e7cddac
[vpr][base] check whether instnace exists in netlist
amin1377 Mar 24, 2025
92f42a1
apply comments
amin1377 Mar 24, 2025
2c604bd
make format
amin1377 Mar 24, 2025
518caeb
[vpr][place] add skip anneal option
amin1377 Mar 25, 2025
01ce5d5
[vpr][place] pass skip_anneal to placer
amin1377 Mar 25, 2025
f47d752
[vpr][place] update constraint doc
amin1377 Mar 26, 2025
bcc5058
[vpr][place] minor update to the doc
amin1377 Mar 26, 2025
64bf3b4
Merge pull request #2946 from verilog-to-routing/3d_sb
soheilshahrouz Mar 26, 2025
16b900f
Merge pull request #2953 from verilog-to-routing/floorplan_doc
vaughnbetz Mar 26, 2025
e36c1b7
[vtr][script] add run dir to parse script
amin1377 Mar 30, 2025
332a9b6
Merge pull request #2951 from verilog-to-routing/fix_device_util_report
AlexandreSinger Mar 31, 2025
aad848b
[script] remove get_latest_run_dir_number out of util
amin1377 Mar 31, 2025
f415c18
[script] use run dir name instead of only accepting the run dir num
amin1377 Mar 31, 2025
82a6ba1
[script] rename to set_global_run_dir
amin1377 Mar 31, 2025
cd3c985
make format-py
amin1377 Mar 31, 2025
5a9fa88
fix formatting issue
amin1377 Mar 31, 2025
0ab91a9
[script] fix when run dir is not found
amin1377 Mar 31, 2025
223386a
make format-py
amin1377 Mar 31, 2025
bbdfbb3
fix python lint
amin1377 Mar 31, 2025
0c7800b
add NestedNetlistRouter and custom thread pool
duck2 Jan 30, 2025
b5d0d2c
fix formatting issues
amin1377 Mar 31, 2025
927488c
[script] add class methods
amin1377 Mar 31, 2025
d67615f
fix python lint
amin1377 Mar 31, 2025
31a315e
fix pylint
amin1377 Mar 31, 2025
2311863
Merge pull request #2924 from verilog-to-routing/custom-thread-pool
vaughnbetz Mar 31, 2025
731e101
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Mar 31, 2025
f733220
[place] fix the bug to skip anneal when analytic placer is enabled
amin1377 Mar 31, 2025
c0f1269
[place] rename skip_anneal to quench_only
amin1377 Mar 31, 2025
44dea6a
[place] add doc for place_quench_only
amin1377 Mar 31, 2025
a5b27f2
[AP][GlobalPlacment] Added Bound2Bound Solver
AlexandreSinger Mar 21, 2025
96c7fb6
[AP][GlobalPlacement] Updated B2B Solver According to Feedback
AlexandreSinger Mar 31, 2025
c43f4b3
Merge pull request #2952 from verilog-to-routing/skip_anneal
AlexandreSinger Mar 31, 2025
b9a458c
Merge branch 'master' into feature-ap-solver
AlexandreSinger Mar 31, 2025
7697257
[vpr][place] rename get_initial_move_lim to get_place_inner_loop_num_…
amin1377 Mar 31, 2025
37c5fe1
fix a typo
amin1377 Mar 31, 2025
cd91a66
Bump libs/EXTERNAL/libcatch2 from `914aeec` to `76f70b1`
dependabot[bot] Apr 1, 2025
64ab163
Merge pull request #2949 from AlexandreSinger/feature-ap-solver
AlexandreSinger Apr 2, 2025
ba2656d
Merge branch 'master' into ingest_per_edge_delay
soheilshahrouz Apr 2, 2025
03849e4
fix a few typos
soheilshahrouz Apr 2, 2025
04e25e8
added a doxygen comments
soheilshahrouz Apr 2, 2025
a648aab
use VTR_LOGV_ERROR instead of is statements
soheilshahrouz Apr 2, 2025
4115a25
doxygen comment for load_rr_edge_overrides()
soheilshahrouz Apr 2, 2025
97da592
make format
soheilshahrouz Apr 2, 2025
305c46e
only override edge delay and not electrical stuff
soheilshahrouz Apr 2, 2025
b156515
[script] apply comments
amin1377 Apr 2, 2025
f2368fe
[script] rename get_latest_run_dir to get_active_run_dir
amin1377 Apr 2, 2025
6fc1fe5
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 2, 2025
ddd81e6
[AP] Tuned the AP Flow
AlexandreSinger Mar 22, 2025
6634f57
Merge pull request #2961 from AlexandreSinger/feature-ap-tuning
amin1377 Apr 3, 2025
85dfc29
Merge pull request #2956 from verilog-to-routing/dependabot/submodule…
AlexandreSinger Apr 3, 2025
8bc630f
[Prepacker] Moved the Prepacker Out of Try Pack
AlexandreSinger Apr 4, 2025
3f8d8e4
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 4, 2025
27e6bc7
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 4, 2025
880ad26
[script] afix the bug with get_next_run_dir
amin1377 Apr 4, 2025
5049dcf
python lint
amin1377 Apr 4, 2025
e6c296e
[vpr][place] update get_place_inner_loop_num_move comment
amin1377 Apr 4, 2025
d80ee8b
Merge pull request #2954 from verilog-to-routing/parse_run_dir
amin1377 Apr 6, 2025
7e9e587
[vpr][place] prrint number of moves per temp after getting the number
amin1377 Apr 6, 2025
292cd56
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 6, 2025
36ba8da
Merge pull request #2962 from AlexandreSinger/feature-ap-prepacker
amin1377 Apr 6, 2025
b154328
make format
amin1377 Apr 7, 2025
355e7c1
Merge pull request #2955 from verilog-to-routing/move_lim
amin1377 Apr 8, 2025
4157a48
Merge pull request #2923 from AlexandreSinger/feature-vtr-flow-second…
vaughnbetz Apr 8, 2025
1163f30
add a unit test for reading edge override file
soheilshahrouz Apr 9, 2025
dbeec69
Add edge_id() method to find an edge that connects given src and sink…
soheilshahrouz Apr 9, 2025
690244a
replace for loop with edge_id() method that return an edge connecting…
soheilshahrouz Apr 9, 2025
fb5ad75
add doxygen comment for edge_id() method
soheilshahrouz Apr 9, 2025
ebf88f0
verify overridden edge attribute in the unit test
soheilshahrouz Apr 9, 2025
9b6d824
move operator==() and hash function of t_rr_switch_inf to physical_ty…
soheilshahrouz Apr 9, 2025
df627ce
add test_read_rr_edge_override.txt
soheilshahrouz Apr 9, 2025
4110acd
make format
soheilshahrouz Apr 9, 2025
41b8821
add InsertNewlineAtEOF: true to .clang-format
soheilshahrouz Apr 9, 2025
abe0b4c
make format to add new line at EOF
soheilshahrouz Apr 9, 2025
14b562e
Merge branch 'master' into ingest_per_edge_delay
soheilshahrouz Apr 9, 2025
19cdc14
Merge pull request #2967 from verilog-to-routing/temp_add_empty_line_…
soheilshahrouz Apr 9, 2025
010b0ac
init value of false for load_flat_placement
soheilshahrouz Apr 9, 2025
150f634
[Pack][Timing] Abstracted How Timing is Used in the Packer
AlexandreSinger Apr 6, 2025
433a917
Merge pull request #2965 from AlexandreSinger/feature-pack-timing-man…
AlexandreSinger Apr 10, 2025
7ce51f0
Merge branch 'master' into ingest_per_edge_delay
soheilshahrouz Apr 10, 2025
475f528
[AP][Timing] Added Basic Net Weighting
AlexandreSinger Apr 3, 2025
d6fe4b5
Merge pull request #2969 from AlexandreSinger/feature-ap-timing
vaughnbetz Apr 11, 2025
92c1d31
[AP][Test] Added Titan Nightly Test of WL-Driven AP Flow
AlexandreSinger Apr 11, 2025
bae777e
Merge pull request #2971 from AlexandreSinger/feature-ap-nightly-tests
amin1377 Apr 12, 2025
381bce7
enum class for graph type
soheilshahrouz Apr 12, 2025
db541ca
use std::vector for clb_to_clb_directs
soheilshahrouz Apr 12, 2025
e77ea54
doxygen comment for t_unified_to_parallel_seg_index
soheilshahrouz Apr 13, 2025
a816f90
doxygen comment for get_parallel_segs()
soheilshahrouz Apr 13, 2025
3fa32c4
replace t_seg_details* with std::vector<t_seg_details>
soheilshahrouz Apr 13, 2025
7dbe3ff
get_seg_track_counts() returns std::vector<int> + doxygen comment
soheilshahrouz Apr 13, 2025
803ea2f
move local var declarations from beginning of alloc_and_load_seg_deta…
soheilshahrouz Apr 13, 2025
779d9af
pass t_chan_width by reference
soheilshahrouz Apr 14, 2025
b6e97e5
remove get_ordered_seg_track_counts()
soheilshahrouz Apr 14, 2025
787c613
remove t_mux, t_pin_spec, and t_mux_size_distribution structs
soheilshahrouz Apr 14, 2025
2f17f12
add docs for vtr::thread_pool
duck2 Apr 10, 2025
ce17681
Merge pull request #2968 from verilog-to-routing/thread-pool-docs
duck2 Apr 14, 2025
3c0fe91
add is_root_location to grid
soheilshahrouz Apr 14, 2025
d747b16
remove unnecessary calls to clear()
soheilshahrouz Apr 14, 2025
2da44e5
[AP][InitialPlacement] Improved Initial Placement
AlexandreSinger Apr 12, 2025
a5980f2
move t_seg_details, t_chan_seg_details, and t_chan_details to rr_types.h
soheilshahrouz Apr 14, 2025
c8857cc
fix compilation error in test_connection router and the warning in rr…
soheilshahrouz Apr 14, 2025
5090124
Merge pull request #2975 from AlexandreSinger/feature-ap-initial-placer
AlexandreSinger Apr 14, 2025
06e0a34
move t_sblock_pattern to rr_types.h
soheilshahrouz Apr 14, 2025
1b860d1
make format
soheilshahrouz Apr 14, 2025
7ade605
[vpr][place] remove get_net_wirelength_from_layer_bb_ from netcosthan…
amin1377 Apr 15, 2025
5f163bd
[vpr][place] make get_net_wirelength_from_layer_bb_ static function a…
amin1377 Apr 15, 2025
6314262
[vpr][place] use appropiate wirelength est function
amin1377 Apr 15, 2025
ea8d94d
make format
amin1377 Apr 15, 2025
5b06248
[test] add strong 3d
amin1377 Apr 15, 2025
bb23e6c
fix signal 6 in stratix 10 arch strong test
soheilshahrouz Apr 15, 2025
94e24be
Merge remote-tracking branch 'origin/master' into ingest_per_edge_delay
soheilshahrouz Apr 15, 2025
9f06be2
apply PR comments
soheilshahrouz Apr 15, 2025
5da6cf7
add the requested comments
soheilshahrouz Apr 15, 2025
8c960f9
update file_formats.rst
soheilshahrouz Apr 15, 2025
c71a2bc
add --read_rr_edge_override to command_line_usage.rst
soheilshahrouz Apr 15, 2025
eac8bfc
remove duplicate text in command_line_usage.rst
soheilshahrouz Apr 15, 2025
095d10e
[vpr][place] apply review comments
amin1377 Apr 15, 2025
78ceae4
make format
amin1377 Apr 15, 2025
0f672da
make format
amin1377 Apr 15, 2025
1485ed5
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 16, 2025
0b1c8ae
Merge branch 'master' into temp_clean_rrgraph_gen
soheilshahrouz Apr 16, 2025
93c5c39
[vpr][tileable] add include
amin1377 Apr 16, 2025
b88848b
remove unused function linear_regression_vector()
soheilshahrouz Apr 16, 2025
d1f794e
add write_channel_occupancy_to_file()
soheilshahrouz Apr 16, 2025
9ee1ba7
write channel coordinate and occupancy percentage to file
soheilshahrouz Apr 16, 2025
3731d60
make columns aligns in channel utilization files
soheilshahrouz Apr 16, 2025
31b67f2
update submodule
amin1377 Apr 16, 2025
b7b04f4
make format
amin1377 Apr 16, 2025
b56c32a
[libs][arch] return -1 if valid index is not found
amin1377 Apr 16, 2025
1206c72
make format
soheilshahrouz Apr 16, 2025
4186cc5
[libs][arch] comment unused vars
amin1377 Apr 16, 2025
1dff246
Merge pull request #2977 from verilog-to-routing/temp_clean_rrgraph_gen
vaughnbetz Apr 16, 2025
16c1081
refactor the code to use the same code for both x and y channels
soheilshahrouz Apr 16, 2025
9e83292
Merge branch 'master' into temp_chann_util_report
soheilshahrouz Apr 16, 2025
90b8b11
[libs][pugiutil] delete pointer
amin1377 Apr 16, 2025
53b1c34
[libs][pugiutil] format issue
amin1377 Apr 16, 2025
f4ae24a
fix format
amin1377 Apr 16, 2025
b64afde
[libs][archfpga] comment parse_pin_name
amin1377 Apr 16, 2025
de8f8e0
[libs][encrypt] break the line to read file
amin1377 Apr 16, 2025
6d7179f
[vpr][base] call setupvipinf if vib_infs is not empty
amin1377 Apr 16, 2025
661debe
Merge pull request #2985 from verilog-to-routing/temp_chann_util_report
amin1377 Apr 16, 2025
33e4a94
[libs][encrypt] initialize plaintext only if file is open
amin1377 Apr 16, 2025
b996cc3
Merge branch 'master' into fix_3d_test
amin1377 Apr 17, 2025
1b7bfeb
[libs][encrypt] use rdbuf to read a file to avoid gcc-13 warning
amin1377 Apr 17, 2025
1e62cce
[libs][decrypt] rading a file in safe way to prevent gcc13 warning
amin1377 Apr 17, 2025
7289a79
[vpr][vib_grid] fix type name if type is nullptr
amin1377 Apr 17, 2025
c47e039
[vpr][tileable] resize if segment inf size is not zero
amin1377 Apr 17, 2025
c3c65be
[vpr][tileable] use empty method instead of checking size
amin1377 Apr 17, 2025
237d661
[vpr][tileable] set the size when defining the vector (gcc warning)
amin1377 Apr 17, 2025
84ed5da
fix format
amin1377 Apr 17, 2025
2f5e240
Merge pull request #2980 from verilog-to-routing/fix_3d_test
soheilshahrouz Apr 17, 2025
e07eee7
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 17, 2025
2bf8dec
Add Github action to close stale issues
AmirhosseinPoolad Apr 15, 2025
41427ae
Add documentation for automatic issue closure
AmirhosseinPoolad Apr 17, 2025
4c65cef
[test] fix strong constraint
amin1377 Apr 17, 2025
a9043e0
[lib][arch] check num_interconnect is bigger than zero
amin1377 Apr 17, 2025
0357aa4
Merge pull request #2981 from verilog-to-routing/ci_stale_issue
AlexandreSinger Apr 18, 2025
faecc12
[vpr][route] add a condition to not increment delta_seg if the segmen…
amin1377 Apr 18, 2025
690cc63
[vpr][route] fix max seg idx
amin1377 Apr 18, 2025
530a97d
fix formatting
amin1377 Apr 18, 2025
b44e616
Change some internal packer APIs to not use C-style arrays
AmirhosseinPoolad Apr 17, 2025
fbb2d1c
pass by reference and typo
soheilshahrouz Apr 17, 2025
9ba0718
Clean up prepacker
AmirhosseinPoolad Apr 17, 2025
313a984
Change vector variable name to be more inline with the current style
AmirhosseinPoolad Apr 17, 2025
f81f501
remove scratch vectors from Move context
soheilshahrouz Apr 18, 2025
e3380ce
Merge pull request #2987 from verilog-to-routing/pack_remove_c_arr
AlexandreSinger Apr 19, 2025
b4c030f
NetCostHandler is the owner of all bb-related data
soheilshahrouz Apr 19, 2025
bc0ca83
remove PlacerMoveContext
soheilshahrouz Apr 19, 2025
0c32054
define MoveGenerator::first_rlim
soheilshahrouz Apr 19, 2025
6e4d814
Merge branch 'master' into temp_remove_place_move_ctx
soheilshahrouz Apr 19, 2025
2848a32
use #pragma once in move generator header files
soheilshahrouz Apr 19, 2025
9aa55bf
make format
soheilshahrouz Apr 19, 2025
2ef555f
Merge branch 'master' into ingest_per_edge_delay
soheilshahrouz Apr 19, 2025
4c8d908
fix typo
soheilshahrouz Apr 19, 2025
649f3b6
get_bb_from_scratch_() accepts use_ts as its argument
soheilshahrouz Apr 19, 2025
b013af7
[libs][librrgraph] update echo file of rr graph
amin1377 Apr 20, 2025
b8d0455
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 20, 2025
9db1939
[test][strong] update golden result
amin1377 Apr 20, 2025
345d251
[test] update strong tileable golden result
amin1377 Apr 20, 2025
d390291
explain what RR edge override feature is useful for
soheilshahrouz Apr 20, 2025
40a71cc
[test][tileable] update golden results
amin1377 Apr 20, 2025
8bcf4f4
add comment for MoveGenerator::first_rlim
soheilshahrouz Apr 21, 2025
921b67e
[STA] Updated SDF File Generation to Include Min Delays
AlexandreSinger Apr 16, 2025
e03cd90
[STA] Updated How Un-Initialized Delay Triples are Handled
AlexandreSinger Apr 18, 2025
dfa1bd3
[AP][InitialPlacement] Created Isolated AP Flow
AlexandreSinger Apr 14, 2025
118165e
add doxygen comment for X_coord, Y_coord, and layer_coord
soheilshahrouz Apr 21, 2025
82bc33d
remove X_coord and Y_coord from feasibe_region_move_generator
soheilshahrouz Apr 21, 2025
900e2e2
add comment explaining ts and permanent data members
soheilshahrouz Apr 21, 2025
1706dd4
make format
soheilshahrouz Apr 21, 2025
e4f4f4e
Merge pull request #2986 from AlexandreSinger/feature-open-sta
AlexandreSinger Apr 21, 2025
3663572
Merge pull request #2988 from AlexandreSinger/feature-ap-initial-placer
AlexandreSinger Apr 21, 2025
c881146
Merge pull request #2930 from verilog-to-routing/ingest_per_edge_delay
soheilshahrouz Apr 21, 2025
1b89c8a
[AP] General Fixed/Unfixed Blocks Cleanup
AlexandreSinger Apr 21, 2025
f71176c
Merge pull request #2989 from verilog-to-routing/temp_remove_place_mo…
amin1377 Apr 21, 2025
f3b166e
Remove atom_net global context mutation from packer
AmirhosseinPoolad Apr 21, 2025
735448c
Merge pull request #2984 from verilog-to-routing/wip_remove_mut_globa…
AlexandreSinger Apr 22, 2025
1e479b9
Merge pull request #2990 from AlexandreSinger/feature-ap-fixed-blocks
AlexandreSinger Apr 22, 2025
c97ca21
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
amin1377 Apr 22, 2025
dd08d1e
[vpr][tileable_rr_graph] fix rr_switch usage
amin1377 Apr 22, 2025
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9 changes: 5 additions & 4 deletions .clang-format
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ AllowShortIfStatementsOnASingleLine: true
AllowShortLoopsOnASingleLine: false
AlwaysBreakAfterDefinitionReturnType: None
AlwaysBreakAfterReturnType: None
AlwaysBreakBeforeMultilineStrings: true
AlwaysBreakBeforeMultilineStrings: false
AlwaysBreakTemplateDeclarations: true
BinPackArguments: true
BinPackParameters: false
Expand All @@ -34,7 +34,7 @@ BraceWrapping:
SplitEmptyFunction: false
SplitEmptyRecord: true
SplitEmptyNamespace: true
BreakBeforeBinaryOperators: All
BreakBeforeBinaryOperators: NonAssignment
BreakBeforeBraces: Custom
BreakBeforeInheritanceComma: false
BreakBeforeTernaryOperators: true
Expand Down Expand Up @@ -68,10 +68,11 @@ IncludeIsMainRegex: '([-_](test|unittest))?$'
IndentCaseLabels: true
IndentWidth: 4
IndentWrappedFunctionNames: false
IndentPPDirectives: AfterHash
IndentPPDirectives: None
InsertNewlineAtEOF: true
JavaScriptQuotes: Leave
JavaScriptWrapImports: true
KeepEmptyLinesAtTheStartOfBlocks: false
KeepEmptyLinesAtTheStartOfBlocks: true
MacroBlockBegin: ''
MacroBlockEnd: ''
MaxEmptyLinesToKeep: 1
Expand Down
2 changes: 1 addition & 1 deletion .github/scripts/install_dependencies.sh
Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,7 @@ sudo apt install -y \
clang-16 \
clang-17 \
clang-18 \
clang-format-14 \
clang-format-18 \
libtbb-dev \
openssl

Expand Down
6 changes: 2 additions & 4 deletions .github/workflows/nightly_test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,6 @@ on:
# - '**.md'
# - '**.rst'
workflow_dispatch:
schedule:
- cron: '0 0 * * *' # daily

# We want to cancel previous runs for a given PR or branch / ref if another CI
# run is requested.
Expand Down Expand Up @@ -65,9 +63,9 @@ jobs:
- {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
# - {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""}
- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=OFF", extra_pkgs: ""}
- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DSYNLIG_SYSTEMVERILOG=ON", extra_pkgs: ""}

env:
DEBIAN_FRONTEND: "noninteractive"
Expand Down
106 changes: 106 additions & 0 deletions .github/workflows/nightly_test_manual.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,106 @@
name: NightlyTestManual

# This workflow can only be dispatched.
on:
workflow_dispatch:

# Automatically runs every Sunday 5 AM UTC.
# Results should be ready ~15 hours later (Sunday 8 PM UTC), on time for Monday mornings.
schedule:
- cron: '0 5 * * 0'

# We want to cancel previous runs for a given PR or branch / ref if another CI
# run is requested.
# See: https://docs.github.com/en/actions/using-jobs/using-concurrency
concurrency:
group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
cancel-in-progress: true

env:
# default compiler for all non-compatibility tests
MATRIX_EVAL: "CC=gcc-13 && CXX=g++-13"

jobs:
Run-tests:
# Prevents from running on forks where no custom runners are available
if: ${{ github.repository_owner == 'verilog-to-routing' }}

name: 'Nightly Tests Manual Run'
# This workflow is expected to take around 19 hours. Giving it 24 hours
# before timing out.
timeout-minutes: 1440
runs-on: [self-hosted, Linux, X64, SAVI]

steps:
# Clean previous runs of this workflow.
- name: 'Cleanup build folder'
run: |
rm -rf ./* || true
rm -rf ./.??* || true

# Checkout the VTR repo.
- uses: actions/checkout@v4
with:
submodules: 'true'

# Get the extra benchmarks
- name: 'Get Extra Benchmarks'
run: |
make get_titan_benchmarks
make get_ispd_benchmarks
./dev/upgrade_vtr_archs.sh
make get_symbiflow_benchmarks

# Build VTR using the default build options.
- name: 'Build VTR'
run: |
make -j12
make env
source .venv/bin/activate
pip install -r requirements.txt

# Run all of the nightly tests.
# TODO: We could expose more parallelism if we had one task list which ran
# all of these.
- name: 'Run Nightly Test 1'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test1

- name: 'Run Nightly Test 2'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test2

- name: 'Run Nightly Test 3'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test3


- name: 'Run Nightly Test 4'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test4

- name: 'Run Nightly Test 5'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test5

- name: 'Run Nightly Test 6'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test6

- name: 'Run Nightly Test 7'
if: success() || failure()
run: |
source .venv/bin/activate
./run_reg_test.py -j12 vtr_reg_nightly_test7
31 changes: 31 additions & 0 deletions .github/workflows/stale.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,31 @@
name: 'Close Stale Issues'
on:
schedule:
# Run everyday at 1 PM UTC
- cron: '0 13 * * *'

jobs:
stale:
runs-on: ubuntu-latest
steps:
- uses: actions/stale@v9
with:
# The message to be shown for stale issues
stale-issue-message: 'This issue has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you believe this is still an issue, please add a comment.'
close-issue-message: 'This issue has been marked stale for 15 days and has been automatically closed.'
# If you want to exempt an issue from being marked stale/deleted, label it as 'no-stale'
exempt-issue-labels: 'no-stale'
days-before-issue-stale: 365
days-before-issue-close: 15
# Start from the oldest issues
ascending: true

# The configuration below can be used to allow the same behaviour with PRs.
# Since we currently don't want to close old PRs, it is commented out but
# left here in case we change our mind.

# stale-pr-message: 'This PR has been inactive for a year and has been marked as stale. It will be closed in 15 days if it continues to be stale. If you are still working on this PR, please add a comment.'
# close-pr-message: 'This PR has been marked stale for 15 days and has been automatically closed.'
# exempt-pr-labels: 'no-stale'
# days-before-pr-stale: 365
# days-before-pr-close: 15
3 changes: 2 additions & 1 deletion .github/workflows/test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -89,6 +89,8 @@ jobs:
with:
python-version: 3.10.10
- uses: actions/checkout@v4
with:
submodules: 'true'

- name: Install dependencies
run: ./.github/scripts/install_dependencies.sh
Expand Down Expand Up @@ -439,7 +441,6 @@ jobs:
- { name: 'GCC 11 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-11 && CXX=g++-11', }
- { name: 'GCC 12 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-12 && CXX=g++-12', }
- { name: 'GCC 14 (Ubuntu Noble - 24.04)', eval: 'CC=gcc-14 && CXX=g++-14', }
- { name: 'Clang 15 (Ubuntu Noble - 24.04)', eval: 'CC=clang-15 && CXX=clang++-15', }
- { name: 'Clang 16 (Ubuntu Noble - 24.04)', eval: 'CC=clang-16 && CXX=clang++-16', }
- { name: 'Clang 17 (Ubuntu Noble - 24.04)', eval: 'CC=clang-17 && CXX=clang++-17', }
- { name: 'Clang 18 (Ubuntu Noble - 24.04)', eval: 'CC=clang-18 && CXX=clang++-18', }
Expand Down
4 changes: 3 additions & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
[submodule "libs/EXTERNAL/libcatch2"]
path = libs/EXTERNAL/libcatch2
url = https://github.com/catchorg/Catch2.git

# fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp
[submodule "libs/EXTERNAL/sockpp"]
path = libs/EXTERNAL/sockpp
url = https://github.com/w0lek/sockpp.git # fork where in branch v1.0.0_no_complication_warnings there are compilation warnings fixes for upstream tag v1.0.0 of sockpp
url = https://github.com/w0lek/sockpp.git
1 change: 1 addition & 0 deletions .gitpod.Dockerfile
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@ RUN apt-get update \
python-lxml \
qt5-default \
wget \
default-jre \
&& apt-get clean \
&& rm -rf /var/lib/apt/lists/*

Expand Down
58 changes: 58 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,64 @@ _The following are changes which have been implemented in the VTR master branch

### Removed


## v9.0.0 - 2024-12-23

### Added
* Support for Advanced Architectures:
* 3D FPGA and RAD architectures.
* Architectures with hard Networks-on-Chip (NoCs).
* Distinct horizontal and vertical channel widths and types.
* Diagonal routing wires and other complex wire shapes (L-shaped, T-shaped, ....).

* New Benchmark Suites:
* Koios: A deep-learning-focused benchmark suite with various design sizes.
* Hermes: Benchmarks utilizing hard NoCs.
* TitanNew: Large benchmarks targeting the Stratix 10 architecture.

* Commercial FPGAs Architecture Captures:
* Intel’s Stratix 10 FPGA architecture.
* AMD’s 7-series FPGA architecture.

* Parmys Logic Synthesis Flow:
* Better Verilog language coverage
* More efficient hard block mapping

* VPR Graphics Visualizations:
* New interface for improved usability and underlying graphics rewritten using EZGL/GTK to allow more UI widgets.
* Algorithm breakpoint visualizations for placement and routing algorithm debugging.
* User-guided (manual) placement optimization features.
* Enabled a live connection for client graphical application to VTR engines through sockets (server mode).
* Interactive timing path analysis (IPA) client using server mode.

* Performance Enhancements:
* Parallel router for faster inter-cluster routing or flat routing.

* Re-clustering API to modify packing decisions during the flow.
* Support for floorplanning and placement constraints.
* Unified intra- and inter-cluster (flat) routing.
* Comprehensive web-based VTR utilities and API documentation.

### Changed
* The default values of many command line options (e.g. inner_num is 0.5 instead of 1.0)
* Changes to placement engine
* Smart centroid initial placement algorithm.
* Multiple smart placement directed moves.
* Reinforcement learning-based placement algorithm.
* Changes to routing engine
* Faster lookahead creation.
* More accurate lookahead for large blocks.
* More efficient heap and pruning strategies.
* max `pres_fac` capped to avoid possible numeric issues.


### Fixed
* Many algorithmic and coding bugs are fixed in this release

### Removed
* Breadth-first (non-timing-driven) router.
* Non-linear congestion placement cost.

## v8.0.0 - 2020-03-24

### Added
Expand Down
18 changes: 9 additions & 9 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -61,10 +61,10 @@ option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)

# Allow the user to enable building Yosys
option(WITH_PARMYS "Enable Yosys as elaborator and parmys-plugin as partial mapper" ON)
option(YOSYS_F4PGA_PLUGINS "Enable building and installing Yosys SystemVerilog and UHDM plugins" OFF)
option(SYNLIG_SYSTEMVERILOG "Enable building and installing Synlig SystemVerilog and UHDM plugins" OFF)

set(VTR_VERSION_MAJOR 8)
set(VTR_VERSION_MINOR 1)
set(VTR_VERSION_MAJOR 9)
set(VTR_VERSION_MINOR 0)
set(VTR_VERSION_PATCH 0)
set(VTR_VERSION_PRERELEASE "dev")

Expand Down Expand Up @@ -94,9 +94,9 @@ add_definitions("-DVTR_ASSERT_LEVEL=${VTR_ASSERT_LEVEL}")
include(CheckCXXCompilerFlag)

#
# We require c++17 support
# We require c++20 support
#
set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_STANDARD 20)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_CXX_EXTENSIONS OFF) #No compiler specific extensions

Expand Down Expand Up @@ -161,7 +161,7 @@ else()
"-Wcast-align" #Warn if a cast causes memory alignment changes
"-Wshadow" #Warn if local variable shadows another variable
"-Wformat=2" #Sanity checks for printf-like formatting
"-Wno-format-nonliteral" # But don't worry about non-literal formtting (i.e. run-time printf format strings)
"-Wno-format-nonliteral" # But don't worry about non-literal formatting (i.e. run-time printf format strings)
"-Wlogical-op" #Checks for logical op when bit-wise expected
"-Wmissing-declarations" #Warn if a global function is defined with no declaration
"-Wmissing-include-dirs" #Warn if a user include directory is missing
Expand All @@ -179,10 +179,10 @@ else()
"-Wduplicated-cond" #Warn about identical conditions in if-else chains
"-Wduplicated-branches" #Warn when different branches of an if-else chain are equivalent
"-Wnull-dereference" #Warn about null pointer dereference execution paths
"-Wuninitialized" #Warn about unitialized values
"-Wuninitialized" #Warn about uninitialized values
"-Winit-self" #Warn about self-initialization
"-Wcatch-value=3" #Warn when catch statements don't catch by reference
"-Wextra-semi" #Warn about redudnant semicolons
"-Wextra-semi" #Warn about redundant semicolons
"-Wimplicit-fallthrough=3" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings
#GCC-like optional
#"-Wsuggest-final-types" #Suggest where 'final' would help if specified on a type methods
Expand Down Expand Up @@ -454,7 +454,7 @@ if(${WITH_ODIN})
endif()

# handle cmake params to compile Yosys SystemVerilog/UHDM plugins
if(${YOSYS_F4PGA_PLUGINS})
if(${SYNLIG_SYSTEMVERILOG})
# avoid compiling plugins in case the Parmys frontend is not active
if(NOT ${WITH_PARMYS})
message(SEND_ERROR "Utilizing SystemVerilog/UHDM plugins requires activating Parmys frontend. Please set WITH_PARMYS.")
Expand Down
2 changes: 1 addition & 1 deletion CONTRIBUTING.md
Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ This information helps us to quickly reproduce (and hopefully fix) the issue:

Tell us what version of VTR you are using (e.g. the output of `vpr --version`), which Operating System and compiler you are using, or any other relevant information about where or how you are building/running VTR.

Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker.
Once you've gathered all the information [open an Issue](https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/new?template=bug_report.md) on our issue tracker. Issues that do not have any activity for a year will be automatically marked as stale and will be closed after 15 days of being marked as stale.

If you know how to fix the issue, or already have it coded-up, please also consider [submitting the fix](#submitting-code-to-vtr).
This is likely the fastest way to get bugs fixed!
Expand Down
1 change: 1 addition & 0 deletions Dockerfile
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ RUN apt-get update -qq \
&& apt-get -y install --no-install-recommends \
wget \
ninja-build \
default-jre \
libeigen3-dev \
libtbb-dev \
python3-pip \
Expand Down
4 changes: 2 additions & 2 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -48,14 +48,14 @@ ifeq ($(VERBOSE),1)
override CMAKE_PARAMS := -DVTR_ENABLE_VERBOSE=on ${CMAKE_PARAMS}
endif

# -s : Suppresss makefile output (e.g. entering/leaving directories)
# -s : Suppresses makefile output (e.g. entering/leaving directories)
# --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0)
MAKEFLAGS := -s

SOURCE_DIR := $(PWD)
BUILD_DIR ?= build

#Check for the cmake exectuable
#Check for the cmake executable
CMAKE := $(shell command -v cmake 2> /dev/null)

#Show test log on failures with 'make test'
Expand Down
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