Update OpenFPGA

.github/scripts/hostsetup.sh

@@ -70,6 +70,8 @@ apt install -y \
   g++-9 \
   gcc-9 \
   wget \
+  openssl \
+  libssl-dev \
   libtbb-dev
 
 # installing the latest version of cmake

.github/scripts/install_dependencies.sh

@@ -56,7 +56,8 @@ sudo apt install -y \
   clang-17 \
   clang-18 \
   clang-format-18 \
-  libtbb-dev
+  libtbb-dev \
+  openssl
 
 pip install -r requirements.txt
 

CMakeLists.txt

@@ -31,6 +31,7 @@ option(VTR_ENABLE_SANITIZE "Enable address/leak/undefined-behaviour sanitizers (
 option(VTR_ENABLE_PROFILING "Enable performance profiler (gprof)" OFF)
 option(VTR_ENABLE_COVERAGE "Enable code coverage tracking (gcov)" OFF)
 option(VTR_ENABLE_DEBUG_LOGGING "Enable debug logging" OFF)
+option(VTR_ENABLE_VERSION "Enable version number up-to-date during compilation" ON) 
 option(VTR_ENABLE_VERBOSE "Enable increased debug verbosity" OFF)
 option(SPEC_CPU "Enable SPEC CPU v8 support" OFF)
 

doc/src/vpr/VIB.rst

@@ -0,0 +1,254 @@
+.. _VIB:
+
+VIB Architecture
+============
+The VIB architecture adds modeling support for double-level MUX topology and bent wires. In past, switch blocks have only one level of routing MUXes, whose inputs are driven by outputs of programmable blocks and routing tracks. Now outputs of programmable blocks can shape the first level of routing MUXes, while the inputs of second level involves the outputs of first level and other routing tracks. This can reduce the number and input sizes of routing MUXes.
+
+Figure 1 shows the proposed VIB architecture which is tile-based. Each tile is composed of a CLB and a VIB. Each CLB can interact with the corresponding VIB which contains all the routing programmable switches in one tile. Figure 2 shows an example of the detailed interconnect architecture in VIB. The CLB input muxes and the driving muxes of wire segments can share the same fanins. A routing path of a net with two sinks is presented red in the Figure.
+
+.. figure:: ../Images/VIB.png
+    :align: center 
+    :height: 300
+
+    Figure 1. VIB architecture. The connections between the inputs and outputs of the LB and the routing wires are all implemented within the VIB.
+
+.. figure:: ../Images/double-level.png
+    :align: center
+
+    Figure 2. Double-level MUX topology.
+
+Figure 3 shows the modeling for bent wires. A bent L-length wire is modeled as two segments in CHANX and CHANY respectively connected by a delayless switch. The orange and red arrows represent conterclockwise and clockwise bent wires respectively. The bent wires can connect to both bent and straight wire segments.
+
+.. figure:: ../Images/bent_wires.png
+    :align: center
+
+    Figure 3. Presentation for bent wires.
+
+FPGA Architecture File Modification (.xml)
+--------------------------
+For original tags of FPGA architecture file see :ref:`fpga_architecture_description`.
+
+Modification for ``<segmentlist>`` Tag
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The content within the ``<segmentlist>`` tag consists of a group of ``<segment>`` tags.
+The ``<segment>`` tag and its contents are described below.
+
+.. arch:tag:: <segment axis="{x|y}" name="unique_name" length="int" type="{bidir|unidir}" res_type="{GCLK|GENERAL}" freq="float" Rmetal="float" Cmetal="float">content</segment>
+
+    :req_param content:
+        The switch names and the depopulation pattern as described below.
+
+.. arch:tag:: <sb type="pattern">int list</sb>
+
+.. arch:tag:: <cb type="pattern">int list</cb>
+
+.. arch:tag:: <mux name="string"/>
+
+For bent wires, a new content ``<bent>`` is added in the ``<segment>`` tag.
+
+.. arch:tag:: <cb type="pattern">bent pattern list</cb>
+
+    This tag describes the bent pattern for this particular wire segment.
+    For example, a length 4 wire has a bent pattern of ``- - U``.
+    A ``-`` indicates no bent at this position and a ``U`` indicates a conterclockwise bent at the position. (``D`` indicates a clockwise bent.)
+
+    .. note:: A bent wire should remain consistent in both the x and y axes.
+
+New Added Top Level Tag ``<vib_arch>``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+The content within the ``<vib_arch>`` tag consists of a group of ``<vib>`` tags. Different ``<vib>`` tags describe the paradigms of VIB, which apply to different positions.
+
+.. arch:tag:: <vib name="vib_name" pbtype_name="pbtype_name" vib_seg_group="int" arch_vib_switch="string">content</vib>
+
+    :req_param name:
+        A unique alphanumeric name to identify this VIB type.
+
+    :req_param pbtype_name:
+        The name of the block type (e.g. clb, memory) that this VIB connects to. 
+
+    .. note:: A block (e.g. clb, dsp) is connected to the VIB on its top-right side, so the input and output pins of the block should be on the top or right side.
+
+    :req_param vib_seg_group:
+        The number of the segment types in this VIB. 
+
+    :req_param arch_vib_switch:
+        Name of the mux switch type used to drive wires in the VIB by default, and a custom switch can override this switch type for specific connections if desired.
+
+    :req_param content:
+        The segment groups and the multistage MUX topology as described below.
+
+The ``content`` of ``<vib>`` tag consists of several ``<seg_group>`` tags and a ``<multistage_muxs>`` tag.
+For example:
+
+.. code-block:: xml
+
+    <vib_arch>
+        <vib name="vib0" pbtype_name="clb" vib_seg_group="4" arch_vib_switch="mux0">
+            <seg_group name="L1" track_nums="12"/>
+            <seg_group name="L2" track_nums="20"/>
+            <seg_group name="L4" track_nums="16"/>
+            <seg_group name="L8" track_nums="16"/>
+            <multistage_muxs>
+                <first_stage switch_name="mux0">
+                    ...
+                </first_stage>
+                <second_stage>
+                    ...
+                </second_stage>
+            </multistage_muxs>
+        </vib>
+        <vib name="vib1" pbtype_name="dsp" vib_seg_group="4" arch_vib_switch="mux0">
+            ...
+        </vib>
+    </vib_arch>
+
+.. arch:tag:: <seg_group name="seg_name" track_nums="int"/>
+
+    :req_param name:
+    	The name of the segment in this VIB described in ``<segmentlist>``.
+
+    :req_param track_nums:
+    	The track number of the segment in this VIB.
+
+    .. note:: When using unidirectional segments, the track number of the segment represents the number for one direction. For example, the ``track_nums`` is ``10``, which means total ``20`` tracks of the segment in the channel for both (INC & DEC) directions.
+
+.. arch:tag:: <multistage_muxs>content</multistage_muxs>
+
+    :req_param content:
+    	The detaild information for first and second MUXes.
+
+The ``content`` of ``<multistage_muxs>`` tag consists of a ``<first_stage>`` tag and a ``<secong_stage>`` tag.
+
+.. arch:tag:: <first_stage switch_name="switch_name">content</first_stage>
+
+    :req_param switch_name:
+    	Name of the mux switch type used to drive first stage MUXes in the VIB.
+
+    :req_param content:
+    	The details of each MUX.
+
+The ``content`` of ``<first_stage>`` tag consists of many ``<mux>`` tags.
+
+.. arch:tag:: <mux name="mux_name">content</mux>
+
+    :req_param name:
+    	Name of the MUX.
+
+    :req_param content:
+    	A ``<from>`` tag to describe what pins and wires connect to this MUX.
+
+For example:
+
+.. code-block:: xml
+
+    <first_stage switch_name="mux0">
+        <mux name="f_mux_0">
+            <from>clb.O[0] clb.O[1:3] clb.O[4]</from>
+        </mux>
+        <mux name="f_mux_1">
+            <from>L1.E1 L1.S1 L2.E0</from>
+        </mux>
+        ...
+    </first_stage>
+
+The ``<from>`` tag in ``<mux>`` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment.
+
+.. arch:tag:: <second_stage>content</second_stage>
+
+    :req_param content:
+    	The details of each MUX.
+
+The ``content`` of ``<second_stage>`` tag consists of many ``<mux>`` tags.
+
+.. arch:tag:: <mux name="mux_name">content</mux>
+
+    :req_param name:
+    	Name of the MUX.
+
+    :req_param content:
+        A ``<to>`` tag to describe where this MUX connect to and a ``<from>`` tag to describe what pins and wires connect to this MUX.
+
+For example:
+
+.. code-block:: xml
+
+    <second_stage switch_name="mux0">
+        <mux name="s_mux_0">
+            <to>clb.I[0]</to>
+            <from>clb.O[4] f_mux_0 f_mux_1</from>
+        </mux>
+        <mux name="s_mux_1">
+            <to>L1.E1</to>
+            <from>L1.S2 f_mux_0 f_mux_1</from>
+        </mux>
+        ...
+    </second_stage>
+
+The ``<to>`` tag describes the node this MUX connects to. ``clb.I[*]`` means input pin(s); ``L1.E1`` means the track ``1`` in the ``East`` direction of ``L1`` segment. The ``<from>`` tag in ``<mux>`` describes nodes that connects to the MUX. ``clb.O[*]`` means output pin(s); ``L1.S2`` means the track ``2`` in the ``South`` direction of ``L1`` segment. ``f_mux_0`` means the name of the specific first stage MUX.
+
+Here is a complete example of the ``<vib>`` tag:
+
+.. code-block:: xml
+
+        <vib name="vib_clb" pbtype_name="clb" vib_seg_group="2" arch_vib_switch="mux0">
+            <seg_group name="L1" track_nums="12"/>
+            <seg_group name="L2" track_nums="20"/>
+            <multistage_muxs>
+                <first_stage switch_name="mux0">
+                    <mux name="f_mux_0">
+            		<from>clb.O[0] clb.O[1:3] clb.O[4]</from>
+        	    </mux>
+        	    <mux name="f_mux_1">
+            		<from>L1.E1 L1.S1 L2.E0</from>
+        	    </mux>
+                </first_stage>
+                <second_stage>
+                    <mux name="s_mux_0">
+            		<to>clb.I[0]</to>
+            		<from>clb.O[4] f_mux_0 f_mux_1</from>
+        	    </mux>
+        	    <mux name="s_mux_1">
+            		<to>L1.E1</to>
+            		<from>L1.S2 f_mux_0 f_mux_1</from>
+        	    </mux>
+                </second_stage>
+            </multistage_muxs>
+        </vib>
+
+Its corresponding detailed architecture is shown in Figure 4.
+
+.. figure:: ../Images/vib_example.png
+    :align: center 
+    :height: 600
+
+    Figure 4. The corresponding detaied architecture of the example.
+
+New Added Top Level Tag ``<vib_layout>``
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Content inside this tag specifies VIB grid layout to describe different VIBs applied on different locations.
+
+.. arch:tag:: <fixed_layout name="string">content</fixed_layout>
+
+    :req_param name:
+        The name identifying this VIB grid layout. It should be the same as the corresponding layout name inside the ``<layout>`` tag.
+
+    :req_param content:
+        The content should contain a set of grid location tags. For grid location tags of vib_layout see :ref:`fpga_architecture_description`; ref:`grid_expressions`
+
+For example:
+
+.. code-block:: xml
+
+    <vib_layout>
+		<fixed_layout name="fixed_layout">
+			<perimeter type="vib_IO" priority="101"/>
+			<fill type="vib_clb" priority="10"/>
+			<col type="vib_memory" startx="5" starty="1" priority="100"/>
+			...
+        </fixed_layout>
+    </vib_layout>
+
+In this VIB grid layout, ``perimeter``, ``fill``, ``col`` and so on are tags in original ``<layout>`` tag to describe positions of each type of VIB block. The attibute ``type`` should correspond to the ``name`` of a ``<vib>`` tag in ``<vib_arch>``.
+Besides, the ``pbtype_name`` of corresponding ``<vib>`` must be the same as the physical block type at this position. 
+
+In this example, IO blocks are located on the perimeter of the layout. Memory blocks are on column 5 and CLBs are on the rest positions. The ``vib_io``, ``vib_clb`` and ``vib_memory`` are different types of vib blocks corresponding to IO, CLB and memory blocks respectively.

doc/src/vpr/command_line_usage.rst

@@ -379,7 +379,7 @@ Use the options below to override this default naming behaviour.
 
     .. seealso:: :ref:`Routing Resource XML File <vpr_route_resource_file>`.
 
-.. option:: --read_vpr_constraints <file>
+.. option:: --read_vpr_constraints <file1>:<file2>:...:<fileN>
 
     Reads the :ref:`VPR constraints <vpr_constraints>` that the flow must respect from the specified XML file.
 

doc/src/vpr/index.rst

@@ -60,3 +60,5 @@ The purpose of VPR is to make the packing, placement, and routing stages of the
 
    file_formats
    debug_aids
+
+   VIB

doc/src/vpr/route_constraints.rst

@@ -0,0 +1,44 @@
+
+VPR Route Constraints
+=========================
+.. _vpr_constraints_file:
+VPR supports running flows with route constraints. Route constraints are set on global signals to specify if they should be routed or not. For example, a user may want to route a specific internal clock even clock modeling option is set to not route it.
+
+.. note:: The constraint specified in this file overrides the setting of option "--clock_modeling" if it is specified. A message will be issued in such case: "Route constraint(s) detected and will override clock modeling setting". 
+
+The route constraints should be specified by the user using an XML constraints file format, as described in the section below. 
+
+A Constraints File Example
+--------------------------
+
+.. code-block:: xml
+	:caption: An example of a route constraints file in XML format.
+	:linenos:
+
+	<vpr_constraints tool_name="vpr">
+                <global_route_constraints>
+                        <!-- specify route method for a global pin that needs to be connected globally -->
+                        <set_global_signal name="(int_clk)(.*)" type="clock" route_model="route"/>
+                        <set_global_signal name="clk_ni" type="clock" route_model="ideal"/>
+                        <set_global_signal name="rst" type="reset" route_model="ideal"/>
+                </global_route_constraints>
+	</vpr_constraints>
+
+.. _end:
+
+.. note:: The "route_model" in constraint specified in this file only support "ideal" and "route" only.
+
+Constraints File Format
+-----------------------
+
+VPR has a specific XML format which must be used when creating a route constraints file. The purpose of this constraints file is to specify 
+
+#. The signals that should be constrained for routing
+#. The route model for such signals 
+
+The file is passed as an input to VPR when running with route constraints. When the file is read in, its information is used to guide VPR route or not route such signals.
+
+.. note:: Use the VPR option :vpr:option:`--read_vpr_constraints` to specify the VPR route constraints file that is to be loaded. 
+
+.. note:: Wildcard names of signals are supported to specify a list of signals. The wildcard expression should follow the C/C++ regexpr rule.
+

install_apt_packages.sh

@@ -9,7 +9,9 @@ sudo apt-get install -y \
     bison \
     flex \
     python3-dev \
-    python3-venv
+    python3-venv \
+    openssl \
+    libssl-dev
 
 # Required for graphics
 sudo apt-get install -y \

libs/CMakeLists.txt

@@ -9,6 +9,8 @@ link_libraries(${ADDITIONAL_FLAGS})
 add_subdirectory(libarchfpga)
 add_subdirectory(libvtrutil)
 add_subdirectory(liblog)
+add_subdirectory(libencrypt)
+add_subdirectory(libdecrypt)
 add_subdirectory(libpugiutil)
 add_subdirectory(libvqm)
 add_subdirectory(librtlnumber)