remove : capacity attribute in tile

[markram1729]

Description

Related Issue

#2903

Motivation and Context

How Has This Been Tested?

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed

[AlexandreSinger]

This LGTM, thanks for noticing this! I just had one minor comment.

@vaughnbetz I have checked the code and ensured that this property is not being parsed within VTR:

vtr-verilog-to-routing/libs/libarchfpga/src/read_xml_arch_file.cpp

Lines 2995 to 3013 in 3ef570f

	static void ProcessTileProps(pugi::xml_node Node,
	t_physical_tile_type* PhysicalTileType,
	const pugiutil::loc_data& loc_data) {
	expect_only_attributes(Node, {"name", "width", "height", "area"}, loc_data);
	/* Load type name */
	auto Prop = get_attribute(Node, "name", loc_data).value();
	PhysicalTileType->name = Prop;
	/* Load properties */
	PhysicalTileType->width = get_attribute(Node, "width", loc_data, ReqOpt::OPTIONAL).as_uint(1);
	PhysicalTileType->height = get_attribute(Node, "height", loc_data, ReqOpt::OPTIONAL).as_uint(1);
	PhysicalTileType->area = get_attribute(Node, "area", loc_data, ReqOpt::OPTIONAL).as_float(UNDEFINED);
	if (atof(Prop) < 0) {
	archfpga_throw(loc_data.filename_c_str(), loc_data.line(Node),
	"Area for type %s must be non-negative\n", PhysicalTileType->name.c_str());
	}
	}

The t_physical_tile_type struct does have a member called "capacity"; however, according to the parser this is defined as the sum of the capacities of all sub-tiles in this physical tile type. So I think the change in this PR is correct.

[AlexandreSinger]

LGTM, thank you!

[vaughnbetz]

Thanks!