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Changing subtile selection in the try_centroid_placement of initial_placement #2897

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Merged
merged 11 commits into from
Feb 23, 2025
Merged

Changing subtile selection in the try_centroid_placement of initial_placement #2897

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e0522b0
changed the subtile selection in the initial_placement to prevent
haydar-c Feb 14, 2025
8cc499e
hoisted the subtile selection to find_centroid_loc
haydar-c Feb 17, 2025
489698f
added the selection from available subtiles to hoisted selection
haydar-c Feb 18, 2025
d7d6fc9
changed the config (seed) of the strong_sdc tests of vtr_reg_strong(_…
haydar-c Feb 18, 2025
0dba701
updated the helper find_subtile_in_location structure and comments.
haydar-c Feb 18, 2025
463dd1c
Updates based on the review
haydar-c Feb 19, 2025
6664fcb
changed the task list of vtr_reg_multiclock_odin for
haydar-c Feb 20, 2025
05e2917
Merge branch 'master' into reconstruction_from_flat_placement_dicrepa…
AlexandreSinger Feb 20, 2025
03b820a
simplified find_subtile_in_location, improved commenting and updated …
haydar-c Feb 21, 2025
8765153
stylistic simplification
haydar-c Feb 22, 2025
b308dac
manual QoR update for vtr_reg_multiclock_odin
haydar-c Feb 22, 2025
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73 changes: 60 additions & 13 deletions vpr/src/place/initial_placement.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,23 @@ static bool is_loc_legal(const t_pl_loc& loc,
const PartitionRegion& pr,
t_logical_block_type_ptr block_type);

/**
* @brief Helper function to choose a subtile in specified location if compatible and available one exits.
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the type is compatible and an available one exists.

*
* @param centroid The centroid location at which the subtile will be selected using its x,y, and layer.
* @param block_type Logical block type of the macro head member.
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Logical block type we would like to place here

* @param block_loc_registry Placement block location information. To be filled with the location
* where pl_macro is placed.
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I think you should remove the "To be filled with the location where pl_macro is placed."
I'd just say:
"Information on where other blocks have been placed."

* @param pr The PartitionRegion of the macro head member - represents its floorplanning constraints, is the size of
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I'd just say:
The PartitionRegion of the block we are trying to place - represents its floorplanning constraints; it is the size of the whole chip if the block is not constrained.

* the whole chip if the macro is not constrained.
* @param rng A random number generator to select subtile from available and compatible ones.
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(grammatical nit): a subtile from the available and compatible ones

*/
static void find_subtile_in_location(t_pl_loc& centroid,
t_logical_block_type_ptr block_type,
const BlkLocRegistry& blk_loc_registry,
const PartitionRegion& pr,
vtr::RngContainer& rng);

/**
* @brief Calculates a centroid location for a block based on its placed connections.
*
Expand All @@ -159,7 +176,10 @@ static bool is_loc_legal(const t_pl_loc& loc,
*/
static std::vector<ClusterBlockId> find_centroid_loc(const t_pl_macro& pl_macro,
t_pl_loc& centroid,
const BlkLocRegistry& blk_loc_registry);
const BlkLocRegistry& blk_loc_registry,
t_logical_block_type_ptr block_type,
const PartitionRegion& pr,
vtr::RngContainer& rng);

/**
* @brief Tries to find a nearest location to the centroid location if calculated centroid location is not legal or is occupied.
Expand Down Expand Up @@ -339,6 +359,37 @@ static bool is_loc_legal(const t_pl_loc& loc,
return legal;
}

void find_subtile_in_location(t_pl_loc& centroid,
t_logical_block_type_ptr block_type,
const BlkLocRegistry& blk_loc_registry,
const PartitionRegion& pr,
vtr::RngContainer& rng) {
//check if the location is on chip and legal, if yes try to update subtile
if (is_loc_on_chip({centroid.x, centroid.y, centroid.layer}) && is_loc_legal(centroid, pr, block_type)) {
//finding the subtile location
auto& device_ctx = g_vpr_ctx.device();
const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index];
const auto& type = device_ctx.grid.get_physical_type({centroid.x, centroid.y, centroid.layer});
const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index);

//filter out occupied subtiles
const GridBlock& grid_blocks = blk_loc_registry.grid_blocks();
std::vector<int> available_sub_tiles;
for (int sub_tile : compatible_sub_tiles) {
t_pl_loc pos = {centroid.x, centroid.y, sub_tile, centroid.layer};
if (!grid_blocks.block_at_location(pos)) {
available_sub_tiles.push_back(sub_tile);
}
}

//if there is at least one available subtile, update the centroid and do not change otherwise
if (!available_sub_tiles.empty()) {
centroid.sub_tile = available_sub_tiles[rng.irand((int)available_sub_tiles.size() - 1)];
}
}
}


static bool find_centroid_neighbor(t_pl_loc& centroid_loc,
t_logical_block_type_ptr block_type,
bool search_for_empty,
Expand Down Expand Up @@ -392,7 +443,10 @@ static bool find_centroid_neighbor(t_pl_loc& centroid_loc,

static std::vector<ClusterBlockId> find_centroid_loc(const t_pl_macro& pl_macro,
t_pl_loc& centroid,
const BlkLocRegistry& blk_loc_registry) {
const BlkLocRegistry& blk_loc_registry,
t_logical_block_type_ptr block_type,
const PartitionRegion& pr,
vtr::RngContainer& rng) {
const auto& cluster_ctx = g_vpr_ctx.clustering();
const auto& block_locs = blk_loc_registry.block_locs();

Expand Down Expand Up @@ -485,6 +539,8 @@ static std::vector<ClusterBlockId> find_centroid_loc(const t_pl_macro& pl_macro,
} else {
centroid.layer = head_layer_num;
}
//try to find an available and compatible subtile in that location
find_subtile_in_location(centroid, block_type, blk_loc_registry, pr, rng);
}

return connected_blocks_to_update;
Expand Down Expand Up @@ -553,7 +609,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
if (!flat_placement_info.valid) {
// If a flat placement is not provided, use the centroid of connected
// blocks which have already been placed.
unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry, block_type, pr, rng);
} else {
// If a flat placement is provided, use the flat placement to get the
// centroid.
Expand All @@ -565,7 +621,7 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
// location near the flat placement centroid.
if (!is_loc_on_chip({centroid_loc.x, centroid_loc.y, centroid_loc.layer}) ||
!is_loc_legal(centroid_loc, pr, block_type)) {
unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry);
unplaced_blocks_to_update_their_score = find_centroid_loc(pl_macro, centroid_loc, blk_loc_registry, block_type, pr, rng);
}
}

Expand All @@ -590,15 +646,6 @@ static bool try_centroid_placement(const t_pl_macro& pl_macro,
}

auto& device_ctx = g_vpr_ctx.device();
//choose the location's subtile if the centroid location is legal.
//if the location is found within the "find_centroid_neighbor", it already has a subtile
//we don't need to find one again
if (!neighbor_legal_loc) {
const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index];
const auto& type = device_ctx.grid.get_physical_type({centroid_loc.x, centroid_loc.y, centroid_loc.layer});
const auto& compatible_sub_tiles = compressed_block_grid.compatible_sub_tile_num(type->index);
centroid_loc.sub_tile = compatible_sub_tiles[rng.irand((int)compatible_sub_tiles.size() - 1)];
}
int width_offset = device_ctx.grid.get_width_offset({centroid_loc.x, centroid_loc.y, centroid_loc.layer});
int height_offset = device_ctx.grid.get_height_offset({centroid_loc.x, centroid_loc.y, centroid_loc.layer});
VTR_ASSERT(width_offset == 0);
Expand Down
10 changes: 5 additions & 5 deletions vtr_flow/tasks/regression_tests/vtr_reg_strong/basic_ap/config/golden_results.txt
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
fixed_k6_frac_N8_22nm.xml single_wire.v common 1.48 vpr 75.32 MiB -1 -1 0.06 20584 1 0.02 -1 -1 33044 -1 -1 0 1 0 0 success v8.0.0-12150-gcad6e12c1-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-10T16:46:28 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77128 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 3 0 0 3 75.3 MiB 0.54 0.00 0.2714 -0.2714 -0.2714 nan 0.39 7.531e-06 4.665e-06 6.0433e-05 4.1841e-05 75.3 MiB 0.54 75.3 MiB 0.51 8 16 1 6.79088e+06 0 166176. 575.005 0.14 0.00086755 0.000798741 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.01 0.00 0.04 -1 -1 0.01 0.000788782 0.000736266
fixed_k6_frac_N8_22nm.xml single_ff.v common 1.61 vpr 75.31 MiB -1 -1 0.07 20848 1 0.02 -1 -1 33316 -1 -1 1 2 0 0 success v8.0.0-12150-gcad6e12c1-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-10T16:46:28 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77120 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 9 3 2 4 75.3 MiB 0.53 0.00 0.74674 -1.41136 -0.74674 0.74674 0.40 2.2227e-05 1.4289e-05 0.000109603 8.1227e-05 75.3 MiB 0.53 75.3 MiB 0.52 20 31 1 6.79088e+06 13472 414966. 1435.87 0.24 0.000932074 0.000851211 22510 95286 -1 30 1 2 2 142 35 0.74674 0.74674 -1.43836 -0.74674 0 0 503264. 1741.40 0.03 0.00 0.08 -1 -1 0.03 0.000841905 0.000781813
fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 2.56 vpr 76.11 MiB -1 -1 0.25 21992 3 0.07 -1 -1 36796 -1 -1 32 99 1 0 success v8.0.0-12150-gcad6e12c1-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-10T16:46:28 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 77936 99 130 240 229 1 229 262 17 17 289 -1 unnamed_device -1 -1 922 19536 1095 3280 15161 76.1 MiB 0.68 0.00 1.90502 -125.031 -1.90502 1.90502 0.40 0.000671414 0.000596121 0.0173508 0.0153886 76.1 MiB 0.68 76.1 MiB 0.67 32 2029 19 6.79088e+06 979104 586450. 2029.24 0.49 0.0967068 0.0858868 24814 144142 -1 1797 13 568 837 56998 16456 1.9213 1.9213 -139.939 -1.9213 -0.21204 -0.16867 744469. 2576.02 0.04 0.03 0.12 -1 -1 0.04 0.0364713 0.0327019
fixed_k6_frac_N8_22nm.xml diffeq1.v common 17.46 vpr 78.03 MiB -1 -1 0.39 26984 15 0.32 -1 -1 37600 -1 -1 47 162 0 5 success v8.0.0-12150-gcad6e12c1-dirty release VTR_ASSERT_LEVEL=3 GNU 13.2.0 on Linux-6.8.0-49-generic x86_64 2025-02-10T16:46:28 srivatsan-Precision-Tower-5810 /home/alex/vtr-verilog-to-routing 79904 162 96 817 258 1 740 310 17 17 289 -1 unnamed_device -1 -1 7095 27558 418 7907 19233 78.0 MiB 1.56 0.01 21.5089 -1654.97 -21.5089 21.5089 0.41 0.00201386 0.0017781 0.0639353 0.0570499 78.0 MiB 1.56 78.0 MiB 1.06 66 13667 30 6.79088e+06 2.61318e+06 1.11570e+06 3860.55 12.67 1.01308 0.910151 31150 283249 -1 12086 16 3735 9584 1188962 281307 20.677 20.677 -1595.68 -20.677 0 0 1.39736e+06 4835.16 0.07 0.27 0.27 -1 -1 0.07 0.15436 0.14041
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time
fixed_k6_frac_N8_22nm.xml single_wire.v common 2.21 vpr 74.33 MiB -1 -1 0.11 20252 1 0.04 -1 -1 33084 -1 -1 0 1 0 0 success v8.0.0-12161-g489698f01-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-18T11:17:37 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76116 1 1 0 2 0 1 2 17 17 289 -1 unnamed_device -1 -1 2 3 0 0 3 74.3 MiB 0.69 0.00 0.2714 -0.2714 -0.2714 nan 0.43 1.0929e-05 6.519e-06 7.2568e-05 4.7472e-05 74.3 MiB 0.69 74.3 MiB 0.65 8 16 1 6.79088e+06 0 166176. 575.005 0.22 0.00158287 0.00149989 20206 45088 -1 18 1 1 1 141 56 0.7726 nan -0.7726 -0.7726 0 0 202963. 702.294 0.02 0.00 0.05 -1 -1 0.02 0.00154764 0.00146817
fixed_k6_frac_N8_22nm.xml single_ff.v common 2.52 vpr 74.56 MiB -1 -1 0.11 20760 1 0.05 -1 -1 33204 -1 -1 1 2 0 0 success v8.0.0-12161-g489698f01-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-18T11:17:37 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76348 2 1 3 3 1 3 4 17 17 289 -1 unnamed_device -1 -1 22 9 3 1 5 74.6 MiB 0.80 0.00 0.74674 -1.4524 -0.74674 0.74674 0.51 1.5909e-05 9.307e-06 0.000116047 8.3478e-05 74.6 MiB 0.80 74.6 MiB 0.79 20 27 1 6.79088e+06 13472 414966. 1435.87 0.34 0.0016991 0.00160343 22510 95286 -1 26 1 2 2 102 24 0.691615 0.691615 -1.31306 -0.691615 0 0 503264. 1741.40 0.07 0.00 0.10 -1 -1 0.07 0.00163206 0.00154606
fixed_k6_frac_N8_22nm.xml ch_intrinsics.v common 4.24 vpr 74.95 MiB -1 -1 0.40 21656 3 0.11 -1 -1 37052 -1 -1 32 99 1 0 success v8.0.0-12161-g489698f01-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-18T11:17:37 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 76744 99 130 240 229 1 229 262 17 17 289 -1 unnamed_device -1 -1 883 19536 1068 3887 14581 74.9 MiB 0.98 0.00 1.86512 -124.45 -1.86512 1.86512 0.46 0.000779688 0.000721122 0.0213475 0.0197246 74.9 MiB 0.98 74.9 MiB 0.96 32 1890 11 6.79088e+06 979104 586450. 2029.24 0.75 0.142133 0.121646 24814 144142 -1 1712 13 543 802 57386 17520 1.9213 1.9213 -143.517 -1.9213 -0.04337 -0.04337 744469. 2576.02 0.05 0.07 0.20 -1 -1 0.05 0.066598 0.0611661
fixed_k6_frac_N8_22nm.xml diffeq1.v common 21.52 vpr 76.91 MiB -1 -1 0.62 26520 15 0.62 -1 -1 38216 -1 -1 47 162 0 5 success v8.0.0-12161-g489698f01-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-51-generic x86_64 2025-02-18T11:17:37 haydar-Precision-5820-Tower /home/haydar/vtr-verilog-to-routing 78760 162 96 817 258 1 740 310 17 17 289 -1 unnamed_device -1 -1 7006 24414 236 6771 17407 76.9 MiB 2.93 0.01 21.8698 -1649.28 -21.8698 21.8698 0.59 0.00295868 0.00276614 0.109664 0.102635 76.9 MiB 2.93 76.9 MiB 1.51 60 14847 46 6.79088e+06 2.61318e+06 1.01997e+06 3529.29 13.54 1.39808 1.28894 29998 257685 -1 12402 16 3793 9643 1173029 292327 21.3427 21.3427 -1635.12 -21.3427 0 0 1.27783e+06 4421.56 0.08 0.35 0.26 -1 -1 0.08 0.183513 0.17225
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