verilog-to-routing · Junius00 · Jul 24, 2023 · Jul 24, 2023 · Jul 24, 2023 · Jul 25, 2023
diff --git a/README.md b/README.md
@@ -1,3 +1,36 @@
+# ORCA Special Edition
+This version of VTR is modified by @xilai based on the official version `79a5bc8d163ce15aa195a84459f6350690e1fbf5`. I changed the default compiler, updated Python packages, and updated Yosys and Parmys to fit our purpose. This is tested on ORCA.
+
+## Setup
+1. Install build tools and Python packages. On July 22, 2023, I updated the build tools on ORCA, so if anyone needs to install them on ORCA, there's no need to do it again. (You still need to install python packages)
+
+```
+# some cmds to create a new python environment. I used conda, and it works well, and the official VTR project uses venv, so both should work.
+sudo ./install_apt_packages.sh
+pip install -U -r requirements.txt
+```
+
+2. Compile and verify functionality.
+```
+make CMAKE_PARAMS="-DWITH_PARMYS=ON -DYOSYS_F4PGA_PLUGINS=ON -DYOSYS_PARMYS_PLUGIN=ON"
+./vtr_flow/scripts/run_vtr_task.py regression_tests/vtr_reg_basic/basic_timing
+```
+
+The expected output is:
+```
+k6_N10_mem32K_40nm/single_ff            OK
+k6_N10_mem32K_40nm/single_ff            OK
+k6_N10_mem32K_40nm/single_wire          OK
+k6_N10_mem32K_40nm/single_wire          OK
+k6_N10_mem32K_40nm/diffeq1              OK
+k6_N10_mem32K_40nm/diffeq1              OK
+k6_N10_mem32K_40nm/ch_intrinsics                OK
+k6_N10_mem32K_40nm/ch_intrinsics                OK
+```
+
+## Special Notes
+- F4PGA is currently incompatible with the latest version of Yosys (see issue [here](https://github.com/chipsalliance/yosys-f4pga-plugins/issues/552)); manually downgraded to match the [previous fork](https://github.com/abdelfattah-lab/vtr-verilog-to-routing)'s version. Upgrade when the issue is fixed.
+
 # Verilog to Routing (VTR)
 [![Gitpod Ready-to-Code](https://img.shields.io/badge/Gitpod-Ready--to--Code-blue?logo=gitpod)](https://gitpod.io/#https://github.com/verilog-to-routing/vtr-verilog-to-routing.git)
 [![Build Status](https://github.com/verilog-to-routing/vtr-verilog-to-routing/workflows/Test/badge.svg)](https://github.com/verilog-to-routing/vtr-verilog-to-routing/actions?query=workflow%3ATest) [![Documentation Status](https://readthedocs.org/projects/vtr/badge/?version=latest)](http://docs.verilogtorouting.org/en/latest/)

diff --git a/build-instruction-custom.txt b/build-instruction-custom.txt
@@ -0,0 +1,35 @@
+All changes have already been made, and only run this command to compile the code:
+# first (create a new virtual environment and) install python libs in requirements.txt
+# build with new Parmys + Yosys frontend
+make CMAKE_PARAMS="-DWITH_PARMYS=ON -DYOSYS_F4PGA_PLUGINS=ON -DYOSYS_PARMYS_PLUGIN=ON"
+
+
+
+
+
+@change log:
+requirements.txt:
+    update click to newer version as the bug has alerady been fixed
+yosys/Makefile:
+    change default compiler to gcc as clang does not work well on ORCA
+libs/EXTERNAL/CMakeLists.txt:
+    update to fix system verilog parser bug
+    update Surelog to version 0f9cf823158bf626c8ebbbb29d7685bd7b1592fc
+    update f4pga-plugins to version 73038124b0a2943fe9d591c43f46292bcbf82105
+vtr_flow/scripts/run_vtr_flow.py, vtr_flow/scripts/python_libs/vtr/parmys/parmys.py:
+    add support for top module and search path
+
+
+
+
+
+
+@other misc for reminder:
+
+alias:
+vtrc: activate vtr conda env
+vtrf: run_vtr_flow
+vtrt: run_vtr_task
+
+flow:
+vtrf <circuit_file> <architecture_file>
diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl
@@ -26,10 +26,10 @@ if {$env(PARSER) == "surelog" } {
 	puts "Using Yosys read_systemverilog command"
 	plugin -i systemverilog
 	yosys -import
-	read_systemverilog XXX
+	read_systemverilog -I"SEARCHPATH" -debug XXX
 } elseif {$env(PARSER) == "default" } {
 	puts "Using Yosys read_verilog command"
-	read_verilog -sv -nolatches XXX
+	read_verilog -I"SEARCHPATH" -sv -nolatches XXX
 } else {
 	error "Invalid PARSER"
 }
@@ -39,7 +39,7 @@ scc -select
 select -assert-none %
 select -clear
 
-hierarchy -check -auto-top -purge_lib
+hierarchy -check TOPMODULE -purge_lib
 
 opt_expr
 opt_clean
@@ -80,6 +80,6 @@ opt -fast -noff
 
 stat
 
-hierarchy -check -auto-top -purge_lib
+hierarchy -check TOPMODULE -purge_lib
 
 write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ
diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py
@@ -53,6 +53,8 @@ def init_script_file(
     output_netlist,
     architecture_file_path,
     odin_config_full_path,
+    include_dir='.',
+    top_module='-auto-top'
 ):
     """initializing the raw yosys script file"""
     # specify the input files type
@@ -70,6 +72,8 @@ def init_script_file(
             "CCC": odin_config_full_path,
             "ZZZ": output_netlist,
             "QQQ": architecture_file_path,
+            "SEARCHPATH": include_dir,
+            "TOPMODULE": top_module,
         },
     )
 
@@ -207,6 +211,22 @@ def run(
     # Create a list showing all (.v) and (.vh) files
     circuit_list = create_circuits_list(circuit_file, include_files)
 
+    # parse search directory
+    if ('searchpath' in parmys_args):
+        if (parmys_args['searchpath'] is not None) and (parmys_args['searchpath'] != ''):
+            include_dir = parmys_args['searchpath']
+        del parmys_args['searchpath']
+    else:
+        include_dir = '.'
+
+    # parse top module
+    # NOTE: the default value is '-auto-top'
+    top_module = '-auto-top'
+    if ('topmodule' in parmys_args):
+        if (parmys_args['topmodule'] is not None) and (parmys_args['topmodule'] != ''):
+            top_module = '-top ' + parmys_args['topmodule']
+        del parmys_args['topmodule']
+
     odin_base_config = str(vtr.paths.odin_cfg_path)
 
     # Copy the config file
@@ -230,6 +250,8 @@ def run(
         output_netlist.name,
         architecture_file_path,
         odin_config_full_path,
+        include_dir=include_dir,
+        top_module=top_module
     )
 
     # set the parser

diff --git a/vtr_flow/scripts/run_vtr_flow.py b/vtr_flow/scripts/run_vtr_flow.py
@@ -2,6 +2,7 @@
 """
     Module to run the VTR Flow
 """
+
 import sys
 from pathlib import Path
 import argparse
@@ -11,18 +12,19 @@
 from datetime import datetime
 from collections import OrderedDict
 import os
-
+import os
 # pylint: disable=wrong-import-position, import-error
 sys.path.insert(0, str(Path(__file__).resolve().parent / "python_libs"))
 import vtr
-
 # pylint: enable=wrong-import-position, import-error
 
 BASIC_VERBOSITY = 1
 
 VTR_STAGES = ["odin", "parmys", "abc", "ace", "vpr"]
 
 # pylint: disable=too-few-public-methods
+
+
 class VtrStageArgparseAction(argparse.Action):
     """
     Class to parse the VTR stages to begin and end at.
@@ -370,6 +372,18 @@ def vtr_command_argparser(prog=None):
         + "system-verilog]. The script used the Yosys conventional Verilog"
         + " parser if this argument is not specified.",
     )
+    parmys.add_argument(
+        "-top",
+        default=None,
+        dest="topmodule",
+        help="Specify the name of the module in the design that should be considered as top",
+    )
+    parmys.add_argument(
+        '-search',
+        default=os.getcwd(),
+        dest='searchpath',
+        help='search path for verilog files'
+    )
     #
     # VPR arguments
     #
@@ -732,7 +746,8 @@ def process_parmys_args(args):
     """
     parmys_args = OrderedDict()
     parmys_args["parser"] = args.parser
-
+    parmys_args["topmodule"] = args.topmodule
+    parmys_args['searchpath'] = args.searchpath
     return parmys_args
 
 

diff --git a/yosys/.gitcommit b/yosys/.gitcommit
@@ -1 +1 @@
-dac5bd1983a
+$Format:%h$
diff --git a/yosys/.github/ISSUE_TEMPLATE/bug_report.yml b/yosys/.github/ISSUE_TEMPLATE/bug_report.yml
@@ -34,7 +34,6 @@ body:
         - macOS
         - Windows
         - BSD
-        - WebAssembly
       multiple: true
     validations:
       required: true
@@ -43,7 +42,7 @@ body:
     attributes:
       value: >
         When providing steps to reproduce the issue, please ensure that the issue
-        is reproducible in the current git main of Yosys. Also ensure to
+        is reproducible in the current git master of Yosys. Also ensure to
         provide all necessary source files needed.
 
 

diff --git a/yosys/.github/ISSUE_TEMPLATE/docs_report.yml b/yosys/.github/ISSUE_TEMPLATE/docs_report.yml
diff --git a/yosys/.github/PULL_REQUEST_TEMPLATE.md b/yosys/.github/PULL_REQUEST_TEMPLATE.md
diff --git a/yosys/.github/actions/setup-build-env/action.yml b/yosys/.github/actions/setup-build-env/action.yml
diff --git a/yosys/.github/workflows/codeql.yml b/yosys/.github/workflows/codeql.yml
@@ -14,11 +14,10 @@ jobs:
       run: sudo apt-get install bison flex libreadline-dev tcl-dev libffi-dev
 
     - name: Checkout repository
-      uses: actions/checkout@v4
-      with:
-       submodules: true
+      uses: actions/checkout@v3
+
     - name: Initialize CodeQL
-      uses: github/codeql-action/init@v3
+      uses: github/codeql-action/init@v2
       with:
         languages: cpp
         queries: security-extended,security-and-quality
@@ -27,4 +26,4 @@ jobs:
       run: make yosys -j6
 
     - name: Perform CodeQL Analysis
-      uses: github/codeql-action/analyze@v3
+      uses: github/codeql-action/analyze@v2
diff --git a/yosys/.github/workflows/emcc.yml b/yosys/.github/workflows/emcc.yml
@@ -0,0 +1,18 @@
+name: Emscripten Build
+
+on: [push, pull_request]
+
+jobs:
+  emcc:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: mymindstorm/setup-emsdk@v11
+      - uses: actions/checkout@v3
+      - name: Build
+        run: |
+          make config-emcc
+          make YOSYS_VER=latest
+      - uses: actions/upload-artifact@v3
+        with:
+          name: yosysjs
+          path: yosysjs-latest.zip