yosys_update -> v0.38

yosys/.github/workflows/codeql.yml

@@ -14,10 +14,10 @@ jobs:
       run: sudo apt-get install bison flex libreadline-dev tcl-dev libffi-dev
 
     - name: Checkout repository
-      uses: actions/checkout@v3
+      uses: actions/checkout@v4
 
     - name: Initialize CodeQL
-      uses: github/codeql-action/init@v2
+      uses: github/codeql-action/init@v3
       with:
         languages: cpp
         queries: security-extended,security-and-quality
@@ -26,4 +26,4 @@ jobs:
       run: make yosys -j6
 
     - name: Perform CodeQL Analysis
-      uses: github/codeql-action/analyze@v2
+      uses: github/codeql-action/analyze@v3

yosys/.github/workflows/emcc.yml

@@ -6,13 +6,13 @@ jobs:
   emcc:
     runs-on: ubuntu-latest
     steps:
-      - uses: mymindstorm/setup-emsdk@v11
-      - uses: actions/checkout@v3
+      - uses: mymindstorm/setup-emsdk@v14
+      - uses: actions/checkout@v4
       - name: Build
         run: |
           make config-emcc
           make YOSYS_VER=latest
-      - uses: actions/upload-artifact@v3
+      - uses: actions/upload-artifact@v4
         with:
           name: yosysjs
           path: yosysjs-latest.zip

yosys/.github/workflows/test-linux.yml

@@ -43,6 +43,7 @@ jobs:
           sudo apt-get install $CC $CXX
           echo "CC=$CC" >> $GITHUB_ENV
           echo "CXX=$CXX" >> $GITHUB_ENV
+          echo "CXXFLAGS=-Wp,-D_GLIBCXX_ASSERTIONS" >> $GITHUB_ENV
         env:
           CC: ${{ matrix.compiler }}
 
@@ -78,19 +79,22 @@ jobs:
           $CXX --version
 
       - name: Checkout Yosys
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       - name: Get iverilog
         shell: bash
         run: |
           git clone https://github.com/steveicarus/iverilog.git
+          cd iverilog
+          git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874
+          echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Cache iverilog
         id: cache-iverilog
-        uses: actions/cache@v3
+        uses: actions/cache@v4
         with:
           path: .local/
-          key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
+          key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
 
       - name: Build iverilog
         if: steps.cache-iverilog.outputs.cache-hit != 'true'
@@ -107,10 +111,14 @@ jobs:
         shell: bash
         run: |
           make config-${CC%%-*}
-          make -j${{ env.procs }} CCXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
+          make -j${{ env.procs }} CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
 
       - name: Run tests
         if: (matrix.cpp_std == 'c++11') && (matrix.compiler == 'gcc-11')
         shell: bash
         run: |
           make -j${{ env.procs }} test CXXSTD=${{ matrix.cpp_std }} CC=$CC CXX=$CC LD=$CC
+
+      - name: Log yosys-config output
+        run: |
+          ./yosys-config || true

yosys/.github/workflows/test-macos.yml

@@ -8,7 +8,7 @@ jobs:
     strategy:
       matrix:
         os:
-          - { id: macos-11, name: 'Big Sur' }
+          - { id: macos-13, name: 'Ventura' }
         cpp_std:
           - 'c++11'
           - 'c++17'
@@ -35,19 +35,22 @@ jobs:
           cc --version
 
       - name: Checkout Yosys
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       - name: Get iverilog
         shell: bash
         run: |
           git clone https://github.com/steveicarus/iverilog.git
+          cd iverilog
+          git checkout 192b6aec96fde982e6ddcb28b346d5893aa8e874
+          echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV
 
       - name: Cache iverilog
         id: cache-iverilog
-        uses: actions/cache@v3
+        uses: actions/cache@v4
         with:
           path: .local/
-          key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }}
+          key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }}
 
       - name: Build iverilog
         if: steps.cache-iverilog.outputs.cache-hit != 'true'

yosys/.github/workflows/version.yml

@@ -10,7 +10,7 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
         with:
           fetch-depth: 0
       - name: Take last commit

yosys/.github/workflows/vs.yml

@@ -6,10 +6,10 @@ jobs:
   yosys-vcxsrc:
     runs-on: ubuntu-latest
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - name: Build
         run: make vcxsrc YOSYS_VER=latest
-      - uses: actions/upload-artifact@v3
+      - uses: actions/upload-artifact@v4
         with:
           name: vcxsrc
           path: yosys-win32-vcxsrc-latest.zip
@@ -18,7 +18,7 @@ jobs:
     runs-on: windows-2019
     needs: yosys-vcxsrc
     steps:  
-      - uses: actions/download-artifact@v3
+      - uses: actions/download-artifact@v4
         with:
           name: vcxsrc
           path: .

yosys/.github/workflows/wasi.yml

@@ -0,0 +1,30 @@
+name: WASI Build
+
+on: [push, pull_request]
+
+jobs:
+  wasi:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - name: Build
+        run: |
+          WASI_SDK=wasi-sdk-19.0
+          WASI_SDK_URL=https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz
+          if ! [ -d ${WASI_SDK} ]; then curl -L ${WASI_SDK_URL} | tar xzf -; fi
+
+          mkdir -p build
+          cat > build/Makefile.conf <<END
+          export PATH := $(pwd)/${WASI_SDK}/bin:${PATH}
+          WASI_SYSROOT := $(pwd)/${WASI_SDK}/share/wasi-sysroot
+
+          CONFIG := wasi
+          PREFIX := /
+
+          ENABLE_TCL := 0
+          ENABLE_READLINE := 0
+          ENABLE_PLUGINS := 0
+          ENABLE_ZLIB := 0
+          END
+
+          make -C build -f ../Makefile CXX=clang -j$(nproc)

yosys/.gitignore

@@ -1,9 +1,11 @@
 *.o
 *.d
+*.dwo
 .*.swp
 *.gch
 *.gcda
 *.gcno
+*~
 __pycache__
 /.cproject
 /.project

yosys/CHANGELOG

@@ -2,6 +2,116 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.37 .. Yosys 0.38
+--------------------------
+ * New commands and options
+    - Added option "-tech" to "opt_lut" pass.
+    - Added option "-nokeep_prints" to "hierarchy" pass.
+    - Added option "-nolower" to "async2sync" and "clk2fflogic" pass.
+    - Added option "-lower" to "chformal" pass.
+
+ * Various
+    - Added $check cell to represent assertions with messages.
+    - Allow capturing $print cell output in CXXRTL.
+    - Added API to overwrite existing pass from plugin.
+    - Follow the XDG Base Directory Specification for storing history files.
+    - Without a known top module, derive all deferred modules (hierarchy pass).
+    - Detect and error out on combinational loops in write_aiger.
+
+ * Verific support
+    - Added option "-no-split-complex-ports" to "verific -import".
+
+Yosys 0.36 .. Yosys 0.37
+--------------------------
+ * New commands and options
+    - Added option "-nodisplay" to read_verilog.
+
+ * SystemVerilog
+    - Correct hierarchical path names for structs and unions.
+
+ * Various
+    - Print hierarchy for failed assertions in "sim" pass.
+    - Add "--present-only" option to "yosys-witness" to omit unused signals.
+    - Implement a generic record/replay interface for CXXRTL.
+    - Improved readability of emitted code with "write_verilog".
+
+Yosys 0.35 .. Yosys 0.36
+--------------------------
+ * New commands and options
+    - Added option "--" to pass arguments down to tcl when using -c option.
+    - Added ability on MacOS and Windows to pass options after arguments on cli.
+    - Added option "-cmp2softlogic" to synth_lattice.
+    - Added option "-lowpower" to "booth" pass.
+
+ * QuickLogic support
+    - Added "K6N10f" support.
+    - Added "-nodsp", "-nocarry", "-nobram" and "-bramtypes" options to 
+      "synth_quicklogic" pass.
+    - Added "ql_bram_merge" pass to merge 18K BRAM cells into TDP36K.
+    - Added "ql_bram_types" pass to change TDP36K depending on configuration.
+    - Added "ql_dsp_io_regs" pass to update QL_DSP2 depending on configuration.
+    - Added "ql_dsp_macc" pass to infer multiplier-accumulator DSP cells.
+    - Added "ql_dsp_simd" pass to merge DSP pairs to operate in SIMD mode.
+
+ * ECP5,iCE40 and Gowin support
+    - Enabled abc9 by default, added "-noabc9" option to disable.
+
+ * MachXO3 support
+    - Quality of results improvements.
+    - Enabled "booth" pass by default for it in "synth_lattice".
+
+ * Various
+    - Improved "peepopt" by adding shiftadd pattern support.
+    - Added "--incremental" mode to smtbmc.
+
+Yosys 0.34 .. Yosys 0.35
+--------------------------
+ * Various
+    - Improvements on "peepopt" shiftmul matcher.
+    - Improvements on "ram_style" attributes handling.
+
+ * Verific support
+    - Improved static elaboration for VHDL and mixed HDL designs.
+    - Expose "hdlname" attribute with original module name.
+    - Expose "architecture" attribute with VHDL architecture name.
+
+Yosys 0.33 .. Yosys 0.34
+--------------------------
+ * New commands and options
+    - Added option "-assert" to "sim" pass.
+    - Added option "-noinitstate" to "sim" pass.
+    - Added option "-dont_use" to "abc" pass.
+    - Added "dft_tag" pass to create tagging logic for data flow tracking.
+    - Added "future" pass to resolve future sampled value functions.
+    - Added "booth" pass to map $mul cells to Booth multipliers.
+    - Added option "-booth" to "synth" pass.
+
+ * SystemVerilog
+    - Added support for assignments within expressions, e.g., `x[y++] = z;` or
+      `x = (y *= 2) - 1;`.
+
+ * Verific support
+    - "src" attribute contain full location info.
+    - module parameters are kept after import.
+    - accurate access order semantics in memory inference.
+    - better "bind" support for mixed language projects.
+
+ * Various
+    - "show" command displays dot instead of box for wire aliases.
+
+Yosys 0.32 .. Yosys 0.33
+--------------------------
+ * Various
+    - Added "$print" cell, produced by "$display" and "$write"
+      Verilog tasks.
+    - Added "$print" cell handling in CXXRTL.
+
+ * Lattice FPGA support
+    - Added generic "synth_lattice" pass (for now MachXO2/XO3/XO3D)
+    - Removed "synth_machxo2" pass
+    - Pass "ecp5_gsr" renamed to "lattice_gsr"
+    - "synth_machxo2" equivalent is "synth_lattice -family xo2"
+
 Yosys 0.31 .. Yosys 0.32
 --------------------------
  * Verific support