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This is a fix to avoid division by zero in initial_placement. #2227

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Merged
merged 3 commits into from
Apr 27, 2023

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hermanschmit
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Description

We successfully adapted VPR to a different build system and compiler, but the execution failed when the code attempted to do a division by zero. Illegal instruction.

Motivation and Context

The prior code worked, but it relied on a floating point division by zero resulting in an "inf" and then being converted to an int. This was sloppy, and relies on particular treatment of a SIGFPE. I think it is much cleaner, and more portable to avoid division if the divisor is zero.

How Has This Been Tested?

Built in our system and tested.

@github-actions github-actions bot added the VPR VPR FPGA Placement & Routing Tool label Jan 14, 2023
@hzeller hzeller requested a review from saaramahmoudi April 26, 2023 17:39
@saaramahmoudi
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saaramahmoudi commented Apr 26, 2023

Thanks for catching that, I think we should merge this. @vaughnbetz
We have a division by zero, which result in something that is not on the chip or an illegal instruction, first case handled throughout the code, second does not.

@vaughnbetz vaughnbetz merged commit 5288a17 into verilog-to-routing:master Apr 27, 2023
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3 participants