[WIP] Librrgraph unit test

[oscarcheng105]

Description

This unit test tests the functionality of librrgraph through I/O tests, specifically rr_graph_reader & rr_graph_writer

Related Issue

Other PRs that may impact RRGraph, #2066, #1999
Require to merge #2101 to process on this plan

Motivation and Context

Routing resource graph (RRGraph) is a critical data structure in VTR project (especially for VPR), which interacts with placer, router and timing/power analyzers. RRGraph models the routing resources of a complete FPGA fabric, including pins, wires and programmable switches.
After PR#2101, we proceed to provide an outline for the testing of Librrgraph.

How Has This Been Tested?

We intend to develop unit tests in librrgraph with the following focus:

Phase 1 (I/O Tests)

Goal:

• Check correctness of I/O equivalence and ensure total syntax coverage.

Methodology:

• Read RRGraph (XML) from a file, write to a file and read back (I/O equivalence)
• Generate RRGraph files of small size and big size (# of nodes: 100~10K)
• Test I/O equivalence with the generated RRGraph files and check total syntax coverage

Deliverables:

• Test codes pushed to github and deployed to CI

Phase 2 (QoR-oriented Checks)

The QoR checks will be implemented in the following steps:

• Mimic the builder behaviors when constructing a rr_graph in memory. In this phase, we will consider typical FPGA architectures
• Benchmarking the runtime (graph build-up) and peak memory usage for RRGraph in small size and big size (#. of nodes: 100~10K, up to the maximum graph size used in Titan benchmarks)
• Establish QoR Test on runtime and peak memory usage, similar to current VTR regression tests

Phase 3 (Titan)

• Tests on titan RRGraph will be delayed due to large file size and extra syntax.

Current Progress

• All test case requires a architecture XML file for setup. Both test_arch_base.xml & test_arch_base.xml models K4_N4_90nm.xml with changes in layout.
• Chan_width is currently set manually in test cases.
• To change # of nodes, change layout dimension in test_arch.xml.
• Base test case complete (rrgraph with 10 nodes in 2x2 grid).
• Test Case with 100 ~ 10k nodes (in progress)
  • TODO: edge linking function for opin_to_track, track_to_track, track_to_ipin.

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed