Move rr_graph_reader & rr_graph_writer to librrgraph. #2101
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,22 +1,24 @@ | ||
| #include "vtr_log.h" | ||
| #include "vtr_memory.h" | ||
| #include "vtr_util.h" | ||
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| #include "vpr_error.h" | ||
| #include "check_rr_graph.h" | ||
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| #include "rr_node.h" | ||
| #include "physical_types_util.h" | ||
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| #include "describe_rr_node.h" | ||
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| /*********************** Subroutines local to this module *******************/ | ||
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| static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const DeviceGrid& grid, RRNodeId inode); | ||
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| static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node); | ||
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| static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid& grid, const t_rr_node& node); | ||
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| static void check_rr_edge(const RRGraphView& rr_graph, const DeviceGrid& grid, const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, int from_node, int from_edge, int to_node); | ||
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| /************************ Subroutine definitions ****************************/ | ||
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@@ -39,17 +41,18 @@ class node_edge_sorter { | |
| } | ||
| }; | ||
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| void check_rr_graph(const RRGraphView& rr_graph, | ||
| const std::vector<t_physical_tile_type>& types, | ||
| const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, | ||
| const DeviceGrid& grid, | ||
| const t_chan_width& chan_width, | ||
| const t_graph_type graph_type, | ||
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| int virtual_clock_network_root_idx) { | ||
| e_route_type route_type = DETAILED; | ||
| if (graph_type == GRAPH_GLOBAL) { | ||
| route_type = GLOBAL; | ||
| } | ||
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| auto total_edges_to_node = std::vector<int>(rr_graph.num_nodes()); | ||
| auto switch_types_from_current_to_node = std::vector<unsigned char>(rr_graph.num_nodes()); | ||
| const int num_rr_switches = rr_graph.num_rr_switches(); | ||
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@@ -66,14 +69,14 @@ void check_rr_graph(const t_graph_type graph_type, | |
| } | ||
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| // Virtual clock network sink is special, ignore. | ||
| if (virtual_clock_network_root_idx == int(inode)) { | ||
| continue; | ||
| } | ||
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| t_rr_type rr_type = rr_graph.node_type(rr_node); | ||
| int num_edges = rr_graph.num_edges(RRNodeId(inode)); | ||
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| check_rr_node(rr_graph, rr_indexed_data, grid, chan_width, route_type, inode); | ||
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| /* Check all the connectivity (edges, etc.) information. */ | ||
| edges.resize(0); | ||
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@@ -89,7 +92,7 @@ void check_rr_graph(const t_graph_type graph_type, | |
| inode, to_node); | ||
| } | ||
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| check_rr_edge(rr_graph, grid, rr_indexed_data, inode, iedge, to_node); | ||
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| edges.emplace_back(to_node, iedge); | ||
| total_edges_to_node[to_node]++; | ||
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@@ -181,7 +184,7 @@ void check_rr_graph(const t_graph_type graph_type, | |
| } | ||
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| /* Slow test could leave commented out most of the time. */ | ||
| check_unbuffered_edges(rr_graph, inode); | ||
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| //Check that all config/non-config edges are appropriately organized | ||
| for (auto edge : rr_graph.configurable_edges(RRNodeId(inode))) { | ||
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@@ -204,19 +207,19 @@ void check_rr_graph(const t_graph_type graph_type, | |
| * now I check that everything is reachable. */ | ||
| bool is_fringe_warning_sent = false; | ||
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| for (const RRNodeId& rr_node : rr_graph.nodes()) { | ||
| size_t inode = (size_t)rr_node; | ||
| t_rr_type rr_type = rr_graph.node_type(rr_node); | ||
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| if (rr_type != SOURCE) { | ||
| if (total_edges_to_node[inode] < 1 && !rr_node_is_global_clb_ipin(rr_graph, grid, rr_node)) { | ||
| /* A global CLB input pin will not have any edges, and neither will * | ||
| * a SOURCE or the start of a carry-chain. Anything else is an error. | ||
| * For simplicity, carry-chain input pin are entirely ignored in this test | ||
| */ | ||
| bool is_chain = false; | ||
| if (rr_type == IPIN) { | ||
| t_physical_tile_type_ptr type = grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type; | ||
| for (const t_fc_specification& fc_spec : types[type->index].fc_specs) { | ||
| if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) { | ||
| is_chain = true; | ||
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@@ -235,8 +238,8 @@ void check_rr_graph(const t_graph_type graph_type, | |
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| if (!is_chain && !is_fringe && !is_wire) { | ||
| if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) { | ||
| if (has_adjacent_channel(rr_graph, grid, node)) { | ||
| auto block_type = grid[rr_graph.node_xlow(rr_node)][rr_graph.node_ylow(rr_node)].type; | ||
| std::string pin_name = block_type_pin_index_to_name(block_type, rr_graph.node_pin_num(rr_node)); | ||
| /* Print error messages for all the sides that a node may appear */ | ||
| for (const e_side& node_side : SIDES) { | ||
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@@ -268,16 +271,13 @@ void check_rr_graph(const t_graph_type graph_type, | |
| } | ||
| } | ||
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| static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const DeviceGrid& grid, RRNodeId inode) { | ||
| /* Returns true if inode refers to a global CLB input pin node. */ | ||
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| int ipin; | ||
| t_physical_tile_type_ptr type; | ||
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| type = grid[rr_graph.node_xlow(inode)][rr_graph.node_ylow(inode)].type; | ||
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| if (rr_graph.node_type(inode) != IPIN) | ||
| return (false); | ||
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@@ -287,7 +287,12 @@ static bool rr_node_is_global_clb_ipin(RRNodeId inode) { | |
| return type->is_ignored_pin[ipin]; | ||
| } | ||
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| void check_rr_node(const RRGraphView& rr_graph, | ||
| const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, | ||
| const DeviceGrid& grid, | ||
| const t_chan_width& chan_width, | ||
| enum e_route_type route_type, | ||
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| int inode) { | ||
| /* This routine checks that the rr_node is inside the grid and has a valid | ||
| * pin number, etc. | ||
| */ | ||
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@@ -298,7 +303,6 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
| int nodes_per_chan, tracks_per_node, num_edges; | ||
| RRIndexedDataId cost_index; | ||
| float C, R; | ||
| RRNodeId rr_node = RRNodeId(inode); | ||
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| rr_type = rr_graph.node_type(rr_node); | ||
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@@ -311,7 +315,6 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
| cost_index = rr_graph.node_cost_index(rr_node); | ||
| type = nullptr; | ||
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| if (xlow > xhigh || ylow > yhigh) { | ||
| VPR_ERROR(VPR_ERROR_ROUTE, | ||
| "in check_rr_node: rr endpoints are (%d,%d) and (%d,%d).\n", xlow, ylow, xhigh, yhigh); | ||
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@@ -327,13 +330,13 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
| "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); | ||
| } | ||
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| if (!cost_index || (size_t)cost_index >= (size_t)rr_indexed_data.size()) { | ||
| VPR_FATAL_ERROR(VPR_ERROR_ROUTE, | ||
| "in check_rr_node: node %d cost index (%d) is out of range.\n", inode, cost_index); | ||
| } | ||
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| /* Check that the segment is within the array and such. */ | ||
| type = grid[xlow][ylow].type; | ||
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| switch (rr_type) { | ||
| case SOURCE: | ||
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@@ -439,11 +442,11 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
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| case CHANX: | ||
| if (route_type == DETAILED) { | ||
| nodes_per_chan = chan_width.max; | ||
| tracks_per_node = 1; | ||
| } else { | ||
| nodes_per_chan = 1; | ||
| tracks_per_node = chan_width.x_list[ylow]; | ||
| } | ||
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| if (ptc_num >= nodes_per_chan) { | ||
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@@ -459,11 +462,11 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
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| case CHANY: | ||
| if (route_type == DETAILED) { | ||
| nodes_per_chan = chan_width.max; | ||
| tracks_per_node = 1; | ||
| } else { | ||
| nodes_per_chan = 1; | ||
| tracks_per_node = chan_width.y_list[xlow]; | ||
| } | ||
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| if (ptc_num >= nodes_per_chan) { | ||
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@@ -494,13 +497,13 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
| //Don't worry about disconnect PINs which have no adjacent channels (i.e. on the device perimeter) | ||
| bool check_for_out_edges = true; | ||
| if (rr_type == IPIN || rr_type == OPIN) { | ||
| if (!has_adjacent_channel(rr_graph, grid, rr_graph.rr_nodes()[inode])) { | ||
|
There was a problem hiding this comment. Just a mark, rr_nodes() just expose the internal node storage directly to client function, which should be avoid. I suggest to rework this function later. vtr-verilog-to-routing/libs/librrgraph/src/base/rr_graph_view.h Lines 442 to 445 in 7989197 |
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| check_for_out_edges = false; | ||
| } | ||
| } | ||
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| if (check_for_out_edges) { | ||
| std::string info = describe_rr_node(rr_graph, grid, rr_indexed_data, inode); | ||
| VTR_LOG_WARN("in check_rr_node: %s has no out-going edges.\n", info.c_str()); | ||
| } | ||
| } | ||
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@@ -528,7 +531,7 @@ void check_rr_node(int inode, enum e_route_type route_type, const DeviceContext& | |
| } | ||
| } | ||
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| static void check_unbuffered_edges(const RRGraphView& rr_graph, int from_node) { | ||
| /* This routine checks that all pass transistors in the routing truly are * | ||
| * bidirectional. It may be a slow check, so don't use it all the time. */ | ||
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@@ -537,9 +540,6 @@ static void check_unbuffered_edges(int from_node) { | |
| short from_switch_type; | ||
| bool trans_matched; | ||
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| from_rr_type = rr_graph.node_type(RRNodeId(from_node)); | ||
| if (from_rr_type != CHANX && from_rr_type != CHANY) | ||
| return; | ||
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@@ -584,11 +584,10 @@ static void check_unbuffered_edges(int from_node) { | |
| } /* End for all from_node edges */ | ||
| } | ||
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| static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid& grid, const t_rr_node& node) { | ||
| /* TODO: this function should be reworked later to adapt RRGraphView interface | ||
| * once xlow(), ylow(), side() APIs are implemented | ||
| */ | ||
| VTR_ASSERT(rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN); | ||
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| if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT)) //left device edge connects only along block's right side | ||
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@@ -601,9 +600,7 @@ static bool has_adjacent_channel(const t_rr_node& node, const DeviceGrid& grid) | |
| return true; //All other blocks will be surrounded on all sides by channels | ||
| } | ||
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| static void check_rr_edge(const RRGraphView& rr_graph, const DeviceGrid& grid, const vtr::vector<RRIndexedDataId, t_rr_indexed_data>& rr_indexed_data, int from_node, int iedge, int to_node) { | ||
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| //Check that to to_node's fan-in is correct, given the switch type | ||
| int iswitch = rr_graph.edge_switch(RRNodeId(from_node), iedge); | ||
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@@ -617,7 +614,7 @@ static void check_rr_edge(int from_node, int iedge, int to_node) { | |
| std::string msg = "Non-configurable BUFFER type switch must have only one driver. "; | ||
| msg += vtr::string_fmt(" Actual fan-in was %d (expected 1).\n", to_fanin); | ||
| msg += " Possible cause is complex block output pins connecting to:\n"; | ||
| msg += " " + describe_rr_node(rr_graph, grid, rr_indexed_data, to_node); | ||
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| VPR_FATAL_ERROR(VPR_ERROR_ROUTE, msg.c_str()); | ||
| } | ||
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Just a mark here. This function need a refactoring. We should use
RRNodeIdrather thant_rr_nodewhich is now an internal data of RRGraph