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Merged
merged 48 commits into from
Jul 28, 2022
Merged

Pack malloc to new #2084

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ef74b79
initial commit
jmah76 Jun 24, 2022
8e99ecd
cluster_feasibility_filter.cpp
jmah76 Jun 25, 2022
8108924
cluster_placements
jmah76 Jun 25, 2022
ca9a728
cluster_utils
jmah76 Jun 25, 2022
ef28b6e
cluster & lb_type_rr_graph
jmah76 Jun 26, 2022
45f4a29
output_clustering & pb_type_graph_annotations
jmah76 Jun 26, 2022
d80a8b3
pb_type_graph vectors
jmah76 Jun 26, 2022
2d11144
pb_type_graph some mallocs & callocs
jmah76 Jun 26, 2022
1b6daed
more pb_type_graph mallocs & callocs
jmah76 Jun 26, 2022
f0becd3
more pb_type_graph
jmah76 Jun 27, 2022
03af3f5
pb_type_graph clock, input, output pins
jmah76 Jun 27, 2022
40d6557
pb_type_graph most mem
jmah76 Jun 28, 2022
6da52ed
prepack some
jmah76 Jun 28, 2022
caf0b82
prepack.cpp
jmah76 Jun 28, 2022
bbb5356
deleted unwantedfiles
jmah76 Jun 28, 2022
9d0d3c2
formatting
jmah76 Jun 28, 2022
80d639d
fixed QoR fails(?)
jmah76 Jun 28, 2022
10135ae
fixed bad array new length errors
jmah76 Jun 28, 2022
fc15b62
formatting fix
jmah76 Jun 29, 2022
e202d6e
reallocs to vectors
jmah76 Jun 30, 2022
9031bd4
formatting
jmah76 Jun 30, 2022
1cb521d
formatting
jmah76 Jul 1, 2022
047c641
initial commit
jmah76 Jun 24, 2022
16b891b
cluster_feasibility_filter.cpp
jmah76 Jun 25, 2022
697d0b1
cluster_placements
jmah76 Jun 25, 2022
a2df349
cluster_utils
jmah76 Jun 25, 2022
439e202
cluster & lb_type_rr_graph
jmah76 Jun 26, 2022
569d73b
output_clustering & pb_type_graph_annotations
jmah76 Jun 26, 2022
47a0818
pb_type_graph vectors
jmah76 Jun 26, 2022
8048f9c
pb_type_graph some mallocs & callocs
jmah76 Jun 26, 2022
271c73d
more pb_type_graph mallocs & callocs
jmah76 Jun 26, 2022
c5506ea
more pb_type_graph
jmah76 Jun 27, 2022
d05df70
pb_type_graph clock, input, output pins
jmah76 Jun 27, 2022
6c37a2c
pb_type_graph most mem
jmah76 Jun 28, 2022
2b35adb
prepack some
jmah76 Jun 28, 2022
f4ba119
prepack.cpp
jmah76 Jun 28, 2022
05ac251
deleted unwantedfiles
jmah76 Jun 28, 2022
057b77b
formatting
jmah76 Jun 28, 2022
aa4bbbb
fixed QoR fails(?)
jmah76 Jun 28, 2022
8cda78a
fixed bad array new length errors
jmah76 Jun 28, 2022
466c717
formatting fix
jmah76 Jun 29, 2022
e691124
reallocs to vectors
jmah76 Jun 30, 2022
7cbddc7
formatting
jmah76 Jun 30, 2022
c31469a
formatting
jmah76 Jul 1, 2022
2ab89a1
Merge branch 'pack_malloc_to_new' of https://github.com/verilog-to-ro…
jmah76 Jul 1, 2022
5366e76
removed brackets around objs to be deleted
jmah76 Jul 7, 2022
4be872f
formatting
jmah76 Jul 7, 2022
5f46eb7
Merge branch 'master' into pack_malloc_to_new
jmah76 Jul 21, 2022
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76 changes: 22 additions & 54 deletions libs/libarchfpga/src/arch_util.cpp
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -298,7 +298,7 @@ static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_desc
if (type.pb_type) {
if (type.pb_graph_head) {
free_pb_graph(type.pb_graph_head);
vtr::free(type.pb_graph_head);
delete type.pb_graph_head;
}
}
}
Expand All @@ -316,78 +316,46 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {
/* Free ports for pb graph node */
for (i = 0; i < pb_graph_node->num_input_ports; i++) {
for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
if (pb_graph_node->input_pins[i][j].pin_timing)
vtr::free(pb_graph_node->input_pins[i][j].pin_timing);
if (pb_graph_node->input_pins[i][j].pin_timing_del_max)
vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_max);
if (pb_graph_node->input_pins[i][j].pin_timing_del_min)
vtr::free(pb_graph_node->input_pins[i][j].pin_timing_del_min);
if (pb_graph_node->input_pins[i][j].input_edges)
vtr::free(pb_graph_node->input_pins[i][j].input_edges);
if (pb_graph_node->input_pins[i][j].output_edges)
vtr::free(pb_graph_node->input_pins[i][j].output_edges);
if (pb_graph_node->input_pins[i][j].parent_pin_class)
vtr::free(pb_graph_node->input_pins[i][j].parent_pin_class);
delete[] pb_graph_node->input_pins[i][j].parent_pin_class;
}
delete[] pb_graph_node->input_pins[i];
}
for (i = 0; i < pb_graph_node->num_output_ports; i++) {
for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
if (pb_graph_node->output_pins[i][j].pin_timing)
vtr::free(pb_graph_node->output_pins[i][j].pin_timing);
if (pb_graph_node->output_pins[i][j].pin_timing_del_max)
vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_max);
if (pb_graph_node->output_pins[i][j].pin_timing_del_min)
vtr::free(pb_graph_node->output_pins[i][j].pin_timing_del_min);
if (pb_graph_node->output_pins[i][j].input_edges)
vtr::free(pb_graph_node->output_pins[i][j].input_edges);
if (pb_graph_node->output_pins[i][j].output_edges)
vtr::free(pb_graph_node->output_pins[i][j].output_edges);
if (pb_graph_node->output_pins[i][j].parent_pin_class)
vtr::free(pb_graph_node->output_pins[i][j].parent_pin_class);
delete[] pb_graph_node->output_pins[i][j].parent_pin_class;

if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs) {
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
if (pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]) {
vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k]);
}
delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k];
}
vtr::free(pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs);
delete[] pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs;
}

if (pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins)
vtr::free(pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins);
delete[] pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins;
}
delete[] pb_graph_node->output_pins[i];
}
for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
if (pb_graph_node->clock_pins[i][j].pin_timing)
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing);
if (pb_graph_node->clock_pins[i][j].pin_timing_del_max)
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_max);
if (pb_graph_node->clock_pins[i][j].pin_timing_del_min)
vtr::free(pb_graph_node->clock_pins[i][j].pin_timing_del_min);
if (pb_graph_node->clock_pins[i][j].input_edges)
vtr::free(pb_graph_node->clock_pins[i][j].input_edges);
if (pb_graph_node->clock_pins[i][j].output_edges)
vtr::free(pb_graph_node->clock_pins[i][j].output_edges);
if (pb_graph_node->clock_pins[i][j].parent_pin_class)
vtr::free(pb_graph_node->clock_pins[i][j].parent_pin_class);
delete[] pb_graph_node->clock_pins[i][j].parent_pin_class;
}
delete[] pb_graph_node->clock_pins[i];
}

vtr::free(pb_graph_node->input_pins);
vtr::free(pb_graph_node->output_pins);
vtr::free(pb_graph_node->clock_pins);
delete[] pb_graph_node->input_pins;
delete[] pb_graph_node->output_pins;
delete[] pb_graph_node->clock_pins;

vtr::free(pb_graph_node->num_input_pins);
vtr::free(pb_graph_node->num_output_pins);
vtr::free(pb_graph_node->num_clock_pins);
delete[] pb_graph_node->num_input_pins;
delete[] pb_graph_node->num_output_pins;
delete[] pb_graph_node->num_clock_pins;

vtr::free(pb_graph_node->input_pin_class_size);
vtr::free(pb_graph_node->output_pin_class_size);
delete[] pb_graph_node->input_pin_class_size;
delete[] pb_graph_node->output_pin_class_size;

if (pb_graph_node->interconnect_pins) {
for (i = 0; i < pb_graph_node->pb_type->num_modes; i++) {
Expand All @@ -403,19 +371,19 @@ static void free_pb_graph(t_pb_graph_node* pb_graph_node) {

t_interconnect_power* interconn_power = interconn->interconnect_power;
for (int iport = 0; iport < interconn_power->num_input_ports; ++iport) {
vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins[iport]);
delete[] pb_graph_node->interconnect_pins[i][j].input_pins[iport];
}
for (int iport = 0; iport < interconn_power->num_output_ports; ++iport) {
vtr::free(pb_graph_node->interconnect_pins[i][j].output_pins[iport]);
delete[] pb_graph_node->interconnect_pins[i][j].output_pins[iport];
}
vtr::free(pb_graph_node->interconnect_pins[i][j].input_pins);
vtr::free(pb_graph_node->interconnect_pins[i][j].output_pins);
delete[] pb_graph_node->interconnect_pins[i][j].input_pins;
delete[] pb_graph_node->interconnect_pins[i][j].output_pins;
}
vtr::free(pb_graph_node->interconnect_pins[i]);
delete[] pb_graph_node->interconnect_pins[i];
}
}
vtr::free(pb_graph_node->interconnect_pins);
vtr::free(pb_graph_node->pb_node_power);
delete[] pb_graph_node->interconnect_pins;
delete pb_graph_node->pb_node_power;

for (i = 0; i < pb_type->num_modes; i++) {
for (j = 0; j < pb_type->modes[i].num_pb_type_children; j++) {
Expand Down
12 changes: 6 additions & 6 deletions libs/libarchfpga/src/physical_types.h
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -1235,9 +1235,9 @@ class t_pb_graph_pin {
public:
t_port* port = nullptr;
int pin_number = 0;
t_pb_graph_edge** input_edges = nullptr; /* [0..num_input_edges] */
std::vector<t_pb_graph_edge*> input_edges; /* [0..num_input_edges] */
int num_input_edges = 0;
t_pb_graph_edge** output_edges = nullptr; /* [0..num_output_edges] */
std::vector<t_pb_graph_edge*> output_edges; /* [0..num_output_edges] */
int num_output_edges = 0;

t_pb_graph_node* parent_node = nullptr;
Expand All @@ -1256,9 +1256,9 @@ class t_pb_graph_pin {

/* combinational timing information */
int num_pin_timing = 0; /* Number of ipin to opin timing edges*/
t_pb_graph_pin** pin_timing = nullptr; /* timing edge sink pins [0..num_pin_timing-1]*/
float* pin_timing_del_max = nullptr; /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
float* pin_timing_del_min = nullptr; /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
std::vector<t_pb_graph_pin*> pin_timing; /* timing edge sink pins [0..num_pin_timing-1]*/
std::vector<float> pin_timing_del_max; /* primitive ipin to opin max-delay [0..num_pin_timing-1]*/
std::vector<float> pin_timing_del_min; /* primitive ipin to opin min-delay [0..num_pin_timing-1]*/
int num_pin_timing_del_max_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_max_annotated-1]
int num_pin_timing_del_min_annotated = 0; //The list of valid pin_timing_del_max entries runs from [0..num_pin_timing_del_min_annotated-1]

Expand Down Expand Up @@ -1333,7 +1333,7 @@ class t_pb_graph_edge {

/* pack pattern info */
int num_pack_patterns;
const char** pack_pattern_names;
std::vector<const char*> pack_pattern_names;
int* pack_pattern_indices;
bool infer_pattern;

Expand Down
1 change: 1 addition & 0 deletions libs/libvtrutil/src/vtr_memory.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
#include "vtr_memory.h"
#include "vtr_error.h"
#include "vtr_util.h"
#include "vtr_log.h"

#ifndef __GLIBC__
# include <stdlib.h>
Expand Down
12 changes: 6 additions & 6 deletions vpr/src/base/read_netlist.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -751,10 +751,10 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route,
}
}
for (j = 0; j < num_sets; j++) {
free(pin_node[j]);
delete[] pin_node[j];
}
free(pin_node);
free(num_ptrs);
delete[] pin_node;
delete[] num_ptrs;
if (!found) {
vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(Cur),
"Unknown interconnect %s connecting to pin %s.\n",
Expand Down Expand Up @@ -820,10 +820,10 @@ static void processPorts(pugi::xml_node Parent, t_pb* pb, t_pb_routes& pb_route,
}
}
for (j = 0; j < num_sets; j++) {
free(pin_node[j]);
delete[] pin_node[j];
}
free(pin_node);
free(num_ptrs);
delete[] pin_node;
delete[] num_ptrs;
if (!found) {
vpr_throw(VPR_ERROR_NET_F, netlist_file_name, loc_data.line(Cur),
"Unknown interconnect %s connecting to pin %s.\n",
Expand Down
2 changes: 1 addition & 1 deletion vpr/src/base/vpr_context.h
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Original file line number Diff line number Diff line change
Expand Up @@ -322,7 +322,7 @@ struct ClusteringHelperContext : public Context {
t_ext_pin_util_targets target_external_pin_util;

~ClusteringHelperContext() {
free(primitives_list);
delete[] primitives_list;
}
};

Expand Down
14 changes: 7 additions & 7 deletions vpr/src/base/vpr_types.cpp
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Expand Up @@ -236,31 +236,31 @@ void free_cluster_placement_stats(t_cluster_placement_stats* cluster_placement_s
cur = cluster_placement_stats_list[index].tried;
while (cur != nullptr) {
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these lists look like hand-implemented linked lists.

It might be a consideration to implement them with std::list or std::forward_list.

(should be a consideration in a potential separate future PR). Here for now: only important to remove the parenthesis from the delete calls.

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Agree: Jennifer please file a follow-up issue to track this.

next = cur->next_primitive;
free(cur);
delete cur;
cur = next;
}
cur = cluster_placement_stats_list[index].in_flight;
while (cur != nullptr) {
next = cur->next_primitive;
free(cur);
delete cur;
cur = next;
}
cur = cluster_placement_stats_list[index].invalid;
while (cur != nullptr) {
next = cur->next_primitive;
free(cur);
delete cur;
cur = next;
}
for (int j = 0; j < cluster_placement_stats_list[index].num_pb_types; j++) {
cur = cluster_placement_stats_list[index].valid_primitives[j]->next_primitive;
while (cur != nullptr) {
next = cur->next_primitive;
free(cur);
delete cur;
cur = next;
}
free(cluster_placement_stats_list[index].valid_primitives[j]);
delete cluster_placement_stats_list[index].valid_primitives[j];
}
free(cluster_placement_stats_list[index].valid_primitives);
delete[] cluster_placement_stats_list[index].valid_primitives;
}
free(cluster_placement_stats_list);
delete[] cluster_placement_stats_list;
}
5 changes: 3 additions & 2 deletions vpr/src/pack/cluster.cpp
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Expand Up @@ -189,8 +189,9 @@ std::map<t_logical_block_type_ptr, size_t> do_clustering(const t_packer_opts& pa
get_max_cluster_size_and_pb_depth(helper_ctx.max_cluster_size, max_pb_depth);

if (packer_opts.hill_climbing_flag) {
clustering_data.hill_climbing_inputs_avail = (int*)vtr::calloc(helper_ctx.max_cluster_size + 1,
sizeof(int));
clustering_data.hill_climbing_inputs_avail = new int[helper_ctx.max_cluster_size + 1];
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could the hill_climbing_inputs_avail be a std::vector ? They are automatically 0 initialized and we just would call resize(helper_ctx.max_cluster_size + 1) here. (while at it, it might be worthwhile commenting why + 1)

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Should be doable; another issue to file Jennifer since I think we should land this PR first.

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I'll be honest, I don't know why + 1.

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Can't recall either; indexed up to max_cluster_size presumably but I'd have to look at the code to see why.

for (int i = 0; i < helper_ctx.max_cluster_size + 1; i++)
clustering_data.hill_climbing_inputs_avail[i] = 0;
} else {
clustering_data.hill_climbing_inputs_avail = nullptr; /* if used, die hard */
}
Expand Down
43 changes: 32 additions & 11 deletions vpr/src/pack/cluster_feasibility_filter.cpp
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Expand Up @@ -27,6 +27,7 @@
* Date: May 16, 2012
*/

#include <vector>
#include "vtr_assert.h"
#include "vtr_log.h"
#include "vtr_memory.h"
Expand Down Expand Up @@ -95,25 +96,27 @@ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node) {
/* allocate space */
for (i = 0; i < pb_graph_node->num_input_ports; i++) {
for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) {
pb_graph_node->input_pins[i][j].parent_pin_class = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
pb_graph_node->input_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth];
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
pb_graph_node->input_pins[i][j].parent_pin_class[k] = OPEN;
}
}
}
for (i = 0; i < pb_graph_node->num_output_ports; i++) {
for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) {
pb_graph_node->output_pins[i][j].parent_pin_class = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs = (t_pb_graph_pin***)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(t_pb_graph_pin**));
pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
pb_graph_node->output_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth];
pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs = new t_pb_graph_pin**[pb_graph_node->pb_type->depth];
pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins = new int[pb_graph_node->pb_type->depth];
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k] = nullptr;
pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins[k] = 0;
pb_graph_node->output_pins[i][j].parent_pin_class[k] = OPEN;
}
}
}
for (i = 0; i < pb_graph_node->num_clock_ports; i++) {
for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) {
pb_graph_node->clock_pins[i][j].parent_pin_class = (int*)vtr::calloc(pb_graph_node->pb_type->depth, sizeof(int));
pb_graph_node->clock_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth];
for (k = 0; k < pb_graph_node->pb_type->depth; k++) {
pb_graph_node->clock_pins[i][j].parent_pin_class[k] = OPEN;
}
Expand Down Expand Up @@ -261,9 +264,13 @@ static void load_pin_class_by_depth(t_pb_graph_node* pb_graph_node,
if (pb_graph_node->pb_type->depth == depth && !pb_graph_node->is_primitive()) {
/* Record pin class information for cluster */
pb_graph_node->num_input_pin_class = *input_count + 1; /* number of input pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */
pb_graph_node->input_pin_class_size = (int*)vtr::calloc(*input_count + 1, sizeof(int));
pb_graph_node->input_pin_class_size = new int[*input_count + 1];
for (i = 0; i < *input_count + 1; i++) /* zero-initializing */
pb_graph_node->input_pin_class_size[i] = 0;
pb_graph_node->num_output_pin_class = *output_count + 1; /* number of output pin classes discovered + 1 for primitive inputs not reachable from cluster input pins */
pb_graph_node->output_pin_class_size = (int*)vtr::calloc(*output_count + 1, sizeof(int));
pb_graph_node->output_pin_class_size = new int[*output_count + 1];
for (i = 0; i < *output_count + 1; i++) /* zero-initializing */
pb_graph_node->output_pin_class_size[i] = 0;
sum_pin_class(pb_graph_node);
}
}
Expand Down Expand Up @@ -315,10 +322,24 @@ static void expand_pb_graph_node_and_load_output_to_input_connections(t_pb_graph
if (current_pb_graph_pin->is_primitive_pin()
&& current_pb_graph_pin->port->type == IN_PORT) {
reference_pin->num_connectable_primitive_input_pins[depth]++;
reference_pin->list_of_connectable_input_pin_ptrs[depth] = (t_pb_graph_pin**)vtr::realloc(
reference_pin->list_of_connectable_input_pin_ptrs[depth],
reference_pin->num_connectable_primitive_input_pins[depth]
* sizeof(t_pb_graph_pin*));

if (reference_pin->num_connectable_primitive_input_pins[depth] - 1 > 0) {
std::vector<t_pb_graph_pin*> temp(reference_pin->list_of_connectable_input_pin_ptrs[depth],
reference_pin->list_of_connectable_input_pin_ptrs[depth] + reference_pin->num_connectable_primitive_input_pins[depth] - 1);

delete[] reference_pin->list_of_connectable_input_pin_ptrs[depth];
reference_pin->list_of_connectable_input_pin_ptrs[depth] = new t_pb_graph_pin*[reference_pin->num_connectable_primitive_input_pins[depth]];
for (i = 0; i < reference_pin->num_connectable_primitive_input_pins[depth] - 1; i++)
reference_pin->list_of_connectable_input_pin_ptrs[depth][i] = temp[i];

reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth]
- 1]
= current_pb_graph_pin;
}

else {
reference_pin->list_of_connectable_input_pin_ptrs[depth] = new t_pb_graph_pin*[reference_pin->num_connectable_primitive_input_pins[depth]];
}
reference_pin->list_of_connectable_input_pin_ptrs[depth][reference_pin->num_connectable_primitive_input_pins[depth]
- 1]
= current_pb_graph_pin;
Expand Down
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