Pb graph bug fixes #2029
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Pb graph bug fixes #2029
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…itialized - multiply the number of input-output-clock pins by the capacity of the sub_tile
…rilog-to-routing into pb_graph_bug_fixes
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Lots of failures getting the required dependencies: Can you relaunch @amin1377 |
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I re-launched the CI tests, and now it passes all tests. Link |
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1- .gitignore file is changed to accommodate the files generated by Clion IDE.
2- Other than the pb_types defined in xml file, another level of pb_type is added to the structure if the pb_type in the XML file uses a class.
Normal pb_types are initialized in "ProcessPb_Type" function in "libs/libarchfpga/src/read_xml_arch_file.cpp". However, the newly added pb_types are initialized in "alloc_and_load_default_child_for_pb_type" in "libs/libarchfpga/src/arch_util.cpp". Since they are initialized in two different functions, some pb_type members are missed in the second function.
3- Three members of t_physical_tile_type are not initialized properly. Each tile consists of, potentially, several types of sub_tiles. Each sub_tile has a capacity that is equal to the number of that sub_tile in the tile. In the current implementation, only the number of pins of one instance of a sub_tile is added to the corresponding member in tile data structure. There are two possible solutions for this problem: 1- change the name of num_pins to num_inst_pins 2- multiply the number of pins by the capacity of the sub_tile (In this PR, this solution is implemented)
@vaughnbetz