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FPGA Interchange: add constant synthetic tiles #1958

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Merged
merged 5 commits into from
Mar 15, 2022
Merged

FPGA Interchange: add constant synthetic tiles #1958

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69a214b
libs: arch: interchange: handle constant type cell
acomodi Dec 21, 2021
9a65d63
vpr: base: netlist: interchange: fix bus port generation
acomodi Dec 22, 2021
101d8bd
vpr: base: netlist: fixed bottlneck when reading netlist
acomodi Jan 20, 2022
8658bdd
interchange: vpr: update tests
acomodi Feb 7, 2022
724b87e
libs: arch: interchange: add comment on constant blocks
acomodi Feb 23, 2022
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14 changes: 11 additions & 3 deletions libs/libarchfpga/src/physical_types.h
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Original file line number Diff line number Diff line change
Expand Up @@ -795,11 +795,19 @@ struct t_physical_tile_port {
bool is_clock;
bool is_non_clock_global;
int num_pins;
PortEquivalence equivalent = PortEquivalence::NONE;
PortEquivalence equivalent;

int index;
int absolute_first_pin_index;
int port_index_by_type;

t_physical_tile_port() {
is_clock = false;
is_non_clock_global = false;

num_pins = 1;
equivalent = PortEquivalence::NONE;
}
};

/* Describes the type for a logical block
Expand Down Expand Up @@ -1807,8 +1815,8 @@ struct t_arch {
// for the interchange netlist format, to determine which are the constants
// net names and which virtual cell is responsible to generate them.
// The information is present in the device database.
std::string gnd_cell;
std::string vcc_cell;
std::pair<std::string, std::string> gnd_cell;
std::pair<std::string, std::string> vcc_cell;

std::string gnd_net = "$__gnd_net";
std::string vcc_net = "$__vcc_net";
Expand Down
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