vpr: interchange: add interchange netlist reading support

.github/kokoro/continuous/strong_sanitized.cfg

@@ -2,8 +2,8 @@
 
 build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
 
-# 2 hour
-timeout_mins: 120
+# 4 hour
+timeout_mins: 240
 
 action {
   define_artifacts {

.github/kokoro/presubmit/strong_sanitized.cfg

@@ -2,8 +2,8 @@
 
 build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
 
-# 2 hour
-timeout_mins: 120
+# 4 hour
+timeout_mins: 240
 
 action {
   define_artifacts {

.github/kokoro/steps/hostsetup.sh

@@ -36,6 +36,7 @@ echo "Host adding PPAs"
 echo "----------------------------------------"
 wget --no-check-certificate -O - https://apt.kitware.com/keys/kitware-archive-latest.asc 2>/dev/null | sudo apt-key add -
 sudo apt-add-repository 'deb https://apt.kitware.com/ubuntu/ xenial main'
+sudo add-apt-repository ppa:ubuntu-toolchain-r/test
 echo "----------------------------------------"
 
 echo
@@ -55,48 +56,53 @@ sudo apt-get install -y \
         bison \
         build-essential \
         ca-certificates \
+        clang \
         cmake \
         colordiff \
         coreutils \
         curl \
         flex \
+        gawk \
+        gcc-9 \
+        g++-9 \
         git \
         graphviz \
         inkscape \
         jq \
+        libboost-filesystem-dev \
+        libboost-python-dev \
+        libboost-system-dev \
+        libffi-dev \
         libgtk-3-dev \
+        libreadline-dev \
         libx11-dev \
         make \
         ninja-build \
         nodejs \
+        pkg-config \
         psmisc \
         python \
         python3 \
         python3-dev \
         python3-virtualenv \
         python3-yaml \
         qt5-default \
-        virtualenv \
-        clang \
-	    libreadline-dev \
-        gawk \
         tcl-dev \
-        libffi-dev \
+        virtualenv \
         xdot \
-        pkg-config \
-        libboost-system-dev \
-	    libboost-python-dev \
-        libboost-filesystem-dev \
-        zlib1g-dev \
+        zlib1g-dev
         #Don't include libtbb-dev since it may increase memory usage
         #libtbb-dev \
 
 export PATH="$PATH:/home/kbuilder/.local/bin"
 
+export CC=gcc-9
+export CXX=g++-9
+
 pyenv install -f 3.6.3
 pyenv global 3.6.3
 curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py
-python3 get-pip.py   
+python3 get-pip.py
 rm get-pip.py
 python3 -m pip install -r requirements.txt
 

libs/libarchfpga/src/physical_types.h

@@ -1732,6 +1732,12 @@ struct t_clock_arch_spec {
     std::vector<t_clock_connection_arch> clock_connections_arch;
 };
 
+struct t_lut_cell {
+    std::string name;
+    std::string init_param;
+    std::vector<std::string> inputs;
+};
+
 /*   Detailed routing architecture */
 struct t_arch {
     mutable vtr::string_internment strings;
@@ -1750,11 +1756,38 @@ struct t_arch {
     int num_switches;
     t_direct_inf* Directs = nullptr;
     int num_directs = 0;
+
     t_model* models = nullptr;
     t_model* model_library = nullptr;
+
     t_power_arch* power = nullptr;
     t_clock_arch* clocks = nullptr;
 
+    // Constants
+    // VCC and GND cells are special virtual cells that are
+    // used to handle the constant network of the device.
+    //
+    // Similarly, the constant nets are defined to identify
+    // the generic name for the constant network.
+    //
+    // Given that usually, the constants have a dedicated network in
+    // real FPGAs, this information becomes relevant to identify which
+    // nets from the circuit netlist are belonging to the constant network,
+    // and assigned to it accordingly.
+    //
+    // NOTE: At the moment, the constant cells and nets are primarly used
+    // for the interchange netlist format, to determine which are the constants
+    // net names and which virtual cell is responsible to generate them.
+    // The information is present in the device database.
+    std::string gnd_cell;
+    std::string vcc_cell;
+
+    std::string gnd_net = "$__gnd_net";
+    std::string vcc_net = "$__vcc_net";
+
+    // Luts
+    std::vector<t_lut_cell> lut_cells;
+
     //The name of the switch used for the input connection block (i.e. to
     //connect routing tracks to block pins).
     //This should correspond to a switch in Switches

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -122,6 +122,7 @@ struct ArchReader {
     }
 
     void read_arch() {
+        process_luts();
         process_models();
         process_device();
 
@@ -232,6 +233,14 @@ struct ArchReader {
                                "Model output ports can not have combinational sink ports");
             }
 
+            model_port->min_size = 1;
+            model_port->size = 1;
+            if (port.isBus()) {
+                int s = port.getBus().getBusStart();
+                int e = port.getBus().getBusEnd();
+                model_port->size = std::abs(e - s) + 1;
+            }
+
             port_names.insert(std::pair<std::string, enum PORTS>(model_port->name, dir));
             //Add the port
             if (dir == IN_PORT) {
@@ -245,6 +254,25 @@ struct ArchReader {
         }
     }
 
+    void process_luts() {
+        // Add LUT Cell definitions
+        // This is helpful to understand which cells are LUTs
+        auto lut_def = ar_.getLutDefinitions();
+
+        for (auto lut_cell : lut_def.getLutCells()) {
+            t_lut_cell cell;
+            cell.name = lut_cell.getCell().cStr();
+            for (auto input : lut_cell.getInputPins())
+                cell.inputs.push_back(input.cStr());
+
+            auto equation = lut_cell.getEquation();
+            if (equation.isInitParam())
+                cell.init_param = equation.getInitParam().cStr();
+
+            arch_->lut_cells.push_back(cell);
+        }
+    }
+
     // Layout Processing
     void process_layout() {
         auto strList = ar_.getStrList();

libs/libvtrutil/src/vtr_hash.h

@@ -15,6 +15,16 @@ inline void hash_combine(std::size_t& seed, const T& v) {
     seed ^= hasher(v) + 0x9e3779b9 + (seed << 6) + (seed >> 2);
 }
 
+struct hash_pair {
+    template<class T1, class T2>
+    std::size_t operator()(const std::pair<T1, T2>& pair) const noexcept {
+        auto hash1 = std::hash<T1>{}(pair.first);
+        auto hash2 = std::hash<T2>{}(pair.second);
+
+        return hash1 ^ hash2;
+    }
+};
+
 } // namespace vtr
 
 #endif

vpr/src/base/atom_netlist_utils.cpp

@@ -95,7 +95,10 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) {
             AtomPinId pin = *netlist.block_pins(blk_id).begin();
 
             std::string blk_name = netlist.block_name(blk_id);
-            std::string out_name(blk_name.begin() + 4, blk_name.end()); //+4 to trim out: prefix
+
+            std::string out_prefix("out:");
+            int strip_size = blk_name.substr(0, out_prefix.size()) == out_prefix ? out_prefix.size() : 0;
+            std::string out_name(blk_name.begin() + strip_size, blk_name.end()); //+4 to trim out: prefix if present
 
             fprintf(f, "%s%s", INDENT, out_name.c_str());
 
@@ -307,7 +310,7 @@ void print_netlist_as_blif(FILE* f, const AtomNetlist& netlist) {
             ports.push_back(port_id);
         }
 
-        fprintf(f, ".subckt %s \\\n", blk_model->name);
+        fprintf(f, ".subckt %s \\\n", netlist.block_name(blk_id).c_str());
         for (size_t i = 0; i < ports.size(); i++) {
             auto width = netlist.port_width(ports[i]);
             for (size_t j = 0; j < width; ++j) {

vpr/src/base/read_circuit.cpp

@@ -1,5 +1,6 @@
 #include "read_circuit.h"
 #include "read_blif.h"
+#include "read_interchange_netlist.h"
 #include "atom_netlist.h"
 #include "atom_netlist_utils.h"
 #include "echo_files.h"
@@ -21,20 +22,23 @@ static void process_circuit(AtomNetlist& netlist,
 
 static void show_circuit_stats(const AtomNetlist& netlist);
 
-AtomNetlist read_and_process_circuit(e_circuit_format circuit_format,
-                                     const char* circuit_file,
-                                     const t_model* user_models,
-                                     const t_model* library_models,
-                                     e_const_gen_inference const_gen_inference,
-                                     bool should_absorb_buffers,
-                                     bool should_sweep_dangling_primary_ios,
-                                     bool should_sweep_dangling_nets,
-                                     bool should_sweep_dangling_blocks,
-                                     bool should_sweep_constant_primary_outputs,
-                                     int verbosity) {
+AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch) {
+    // Options
+    const char* circuit_file = vpr_setup.PackerOpts.circuit_file_name.c_str();
+    const t_model* user_models = vpr_setup.user_models;
+    const t_model* library_models = vpr_setup.library_models;
+    e_const_gen_inference const_gen_inference = vpr_setup.NetlistOpts.const_gen_inference;
+    bool should_absorb_buffers = vpr_setup.NetlistOpts.absorb_buffer_luts;
+    bool should_sweep_dangling_primary_ios = vpr_setup.NetlistOpts.sweep_dangling_primary_ios;
+    bool should_sweep_dangling_nets = vpr_setup.NetlistOpts.sweep_dangling_nets;
+    bool should_sweep_dangling_blocks = vpr_setup.NetlistOpts.sweep_dangling_blocks;
+    bool should_sweep_constant_primary_outputs = vpr_setup.NetlistOpts.sweep_constant_primary_outputs;
+    bool verbosity = vpr_setup.NetlistOpts.netlist_verbosity;
+
     if (circuit_format == e_circuit_format::AUTO) {
         auto name_ext = vtr::split_ext(circuit_file);
 
+        VTR_LOGV(verbosity, "Circuit file: %s\n", circuit_file);
         if (name_ext[1] == ".blif") {
             circuit_format = e_circuit_format::BLIF;
         } else if (name_ext[1] == ".eblif") {
@@ -49,10 +53,20 @@ AtomNetlist read_and_process_circuit(e_circuit_format circuit_format,
     {
         vtr::ScopedStartFinishTimer t("Load circuit");
 
-        VTR_ASSERT(circuit_format == e_circuit_format::BLIF
-                   || circuit_format == e_circuit_format::EBLIF);
-
-        netlist = read_blif(circuit_format, circuit_file, user_models, library_models);
+        switch (circuit_format) {
+            case e_circuit_format::BLIF:
+            case e_circuit_format::EBLIF:
+                netlist = read_blif(circuit_format, circuit_file, user_models, library_models);
+                break;
+            case e_circuit_format::FPGA_INTERCHANGE:
+                netlist = read_interchange_netlist(circuit_file, arch);
+                break;
+            default:
+                VPR_FATAL_ERROR(VPR_ERROR_ATOM_NETLIST,
+                                "Unable to identify circuit file format for '%s'. Expect [blif|eblif|fpga-interchange]!\n",
+                                circuit_file);
+                break;
+        }
     }
 
     if (isEchoFileEnabled(E_ECHO_ATOM_NETLIST_ORIG)) {

vpr/src/base/read_circuit.h

@@ -5,20 +5,11 @@
 #include "vpr_types.h"
 
 enum class e_circuit_format {
-    AUTO, ///<Infer from file extension
-    BLIF, ///<Strict structural BLIF
-    EBLIF ///<Structural blif with extensions
+    AUTO,            ///<Infer from file extension
+    BLIF,            ///<Strict structural BLIF
+    EBLIF,           ///<Structural blif with extensions
+    FPGA_INTERCHANGE ///<FPGA Interhange logical netlis format
 };
 
-AtomNetlist read_and_process_circuit(const e_circuit_format circuit_format,
-                                     const char* circuit_file,
-                                     const t_model* user_models,
-                                     const t_model* library_models,
-                                     e_const_gen_inference const_gen_inference,
-                                     bool should_absorb_buffers,
-                                     bool should_sweep_dangling_primary_ios,
-                                     bool should_sweep_dangling_nets,
-                                     bool should_sweep_dangling_blocks,
-                                     bool should_sweep_constant_primary_outputs,
-                                     int verbosity);
+AtomNetlist read_and_process_circuit(e_circuit_format circuit_format, t_vpr_setup& vpr_setup, t_arch& arch);
 #endif