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Change place flow in init place#1841

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vaughnbetz merged 69 commits intomasterverilog-to-routing/vtr-verilog-to-routing:masterfrom

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Oct 12, 2021

Commits

Commits on Aug 24, 2021

• Fixed bug - when placing macros during initial placement, did not used to check whether macro had already been placed. Added check.

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Commits on Aug 25, 2021

• Refactored initial placement to place all blocks in the order they were sorted in, rather than placing all macros and then all non-macro blocks

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Commits on Aug 26, 2021

• Tried different way of updating legal_pos for each macro member

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• Update legal_pos and free_locations all at once after placing macros

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Commits on Sep 1, 2021

• Merging master into branch

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• Refactored placing of non-macro blocks to not use legal_pos or free_locations data structures

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Commits on Sep 2, 2021

• Changed exhaustive placement method to use regular grid instead of compressed grid

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• Added messages for debugging

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Commits on Sep 6, 2021

• Fixed bug where blocks were being placed at grid locations that were not root locations and added routine to echo compressed grid

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Commits on Sep 8, 2021

• Fixed for loops to get rid of warnings, deleted unused code in initial placement, and made macros also not use free_locations and legal_pos

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• Made exhaustive placement routines in initial placement use compressed grid rather than regular grid

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Commits on Sep 9, 2021

• Removed unnecessary code in exhaustive placement routine (regular grid ones)

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• Cleaned up initial placement by removing unused code and ran make format

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• Removed unused lines of code in initial placement

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• Uncommented compressed grid echo file name

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Commits on Sep 14, 2021

• Added debug messages to a function that is giving an assertion failure when the assertion level is 4. Doing this so I can run on CI with these messages and see if this is the assertion failure that…

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• Ran make format

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• Removed debug lines

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• Removed two assertions in get_legal_place_loc in initial placement

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• Added new assertions to check that y dim of compressed grid is >= 0 when using it for exhaustive placement

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Commits on Sep 15, 2021

• Added debug messages to see what happens in CI

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• Merge branch 'master' into change_place_flow_in_init_place

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• Added another debug message

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• Merge branch 'change_place_flow_in_init_place' of https://github.com/verilog-to-routing/vtr-verilog-to-routing into change_place_flow_in_init_place

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• Ran make format

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• Modified debug statements

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• Added more debug statements

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• Added more debug messages

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• Added more debug messages - in try_place_macro

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• Added debug messages to check_macro_can_be_placed

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• Added bug fix - in check_macro_can_be_placed, there was no check to see if the member position x and y were negative (this can happen if an offset is applied that takes it into the negative) - adde…

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Commits on Sep 16, 2021

• Removed all of the extra debugging statements

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Commits on Sep 20, 2021

• Cleaned up code by renaming some functions

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Commits on Sep 22, 2021

• Commented out some warnings to make log file shorter. Also changed config for nightly to run just 1 test

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• Adding some log lines to check how much bb_cost is changing

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Commits on Sep 27, 2021

• Made changes to attempt to accomodate for logical pins potentially having multiple physical pins. Also added debug messages to get_non_updateable_bb

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• Added more debugging lines in place moves flow

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• Added debug messages to check whether physical pins updated for blocks of a certain type

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Commits on Sep 28, 2021

• Fixed bug that was happening because physical pins needed to be resynced, removed unnecessary lines (debug messages) and set nightly 1 test config back to normal

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• Uncommented warning log messages

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• Took out debug lines and added comment for bug fix

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• Ran make format

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• Resync physical pins only when needed for each block, rather than every time a new bb needs to be calculated from scratch

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Commits on Sep 29, 2021

• Added comments to new routines in initial placement

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• Changed seeds in some runs that were having a circuit run into a circuit unroutable message on CI

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Commits on Oct 4, 2021

• Merged macro and non-macro cases for initial placement and added more comments

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Commits on Oct 5, 2021

• Updated fix for bug where physical pins mapping was not getting updated enough during initial placement

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• Updated a comment

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• Updated bug fix for syncing physical pins issue. There was one more place that the pins needed to be synced so that there was no issue with checking the placement costs at the end of initial placement

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Commits on Oct 6, 2021

• Updated golden results to let test pass

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• Updated golden result for basic timing test

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• updated some vtr_reg_strong qor results

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• Updated some more vtr_reg_strong qor tests

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• Updated more vtr_reg_strong qor results

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• Updated more vtr_reg_strong qor results

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• Changed function return types to bool where necessary

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• Updated odin basic test golden results

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• Updated qor golden results for titan quick qor in nightly2 reg test

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Commits on Oct 7, 2021

• Update golden results for vtr_reg_qor_chain_predictor_off

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• Updated golden results of some tests in vtr_reg_nightly_test1

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• Updated golden results of power_extended_arch_list test in nightly1

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• Commented out one circuit from a reg test that needs its golden results updated for that circuit - want to check if all tests otherwise pass

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• Removed unneeded comment

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• Updated golden results for power_extended_circuit_list test in nightly1

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• Updated golden results for odin II basic reg test

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• Updated another set of golden results for odin II basic tests

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Commits on Oct 8, 2021

• Increased range of acceptable qor golden result for min chan width routing area

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• Increased range of acceptable qor golden result for crit path routing area

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• Increased range of qor pass requirements for min_chan_width_route_time

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