verilog-to-routing · vaughnbetz · Jul 30, 2021 · Jul 22, 2021 · Jul 22, 2021 · Jul 23, 2021
diff --git a/ODIN_II/verify_odin.sh b/ODIN_II/verify_odin.sh
@@ -1256,6 +1256,9 @@ function run_vtr_reg() {
 	pushd "${VTR_DIR}"  &> /dev/null
 	RELATIVE_PATH_TO_TEST=$(realapath_from "${FILTERED_VTR_TASK_PATH}" "${VTR_REG_DIR}")
 	/usr/bin/env perl run_reg_test.py -j "${_NUMBER_OF_PROCESS}" $(dirname ${RELATIVE_PATH_TO_TEST})
+    if [ _"$?" != "_0" ]; then
+        _exit_with_code "-1"
+    fi
 	popd  &> /dev/null
 }
 

diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/README.md
@@ -0,0 +1,4 @@
+##ODIN-II Regression 
+
+`task_list.txt` in this directory points to a set of tasks in the same directory. These tasks are referred to in  
+[`light_suite`](https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf) which is part of a series of ODIN-II regression tests. `light_suite` is currently being run by CI under the name`odin_reg_basic`. First, Odin specific tests are run then the task_list is run by `run_vtr_task.py`. Thus, the entirety of the flow is tested for `vtr_reg_multiclock` tasks by CI. 
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/func_multiclock/README.md
@@ -0,0 +1 @@
+The tasks inside this directory tests that VTR can correctly handle multi-clock designs in different ways. The default way to handle multiple clocks is iterative. 
diff --git a/...func_multiclock/blanket/config/config.txt → ...func_multiclock/blanket/config/config.txt b/...func_multiclock/blanket/config/config.txt → ...func_multiclock/blanket/config/config.txt
diff --git a/...sks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt b/...sks/regression_tests/vtr_reg_multiclock/func_multiclock/blanket/config/golden_results.txt
@@ -0,0 +1,4 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  error	  odin_synth_time	  max_odin_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_time	  placed_wirelength_est	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	0.26	  	0.01	6744	1	0.02	-1	-1	35528	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	351120	6	1	13	14	2	8	9	4	4	16	  clb	  auto	0	13	0	0	0.875884	-3.21829	-0.875884	0.545	0.01	9.152E-06	6.411E-06	0.00127579	0.000834052	20	13	2	107788	107788	10441.3	652.579	0.02	0.00190451	0.00132149	13	11	27	27	298	166	1.17974	0.545	-3.80732	-1.17974	0	0	13748.8	859.301	0	0	0.000371941	0.000300732	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	0.37	  	0.02	7180	1	0.02	-1	-1	35560	-1	-1	2	3	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	351456	3	1	25	26	2	8	6	4	4	16	  clb	  auto	0.01	16	0	0	0.571	-8.56916	-0.571	0.557849	0.01	2.6811E-05	1.912E-05	0.000267223	0.000232957	20	21	4	107788	107788	10441.3	652.579	0.02	0.00146154	0.00126639	14	2	7	7	87	53	0.639606	0.557849	-8.83917	-0.639606	0	0	13748.8	859.301	0	0	0.000657086	0.000610546	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	0.24	  	0.01	6708	1	0	-1	-1	33668	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	352744	6	2	10	12	2	8	10	4	4	16	  clb	  auto	0	12	0	0	0.543757	-1.83465	-0.543757	  nan	0.01	7.375E-06	4.815E-06	0.000820477	0.000473849	20	15	6	107788	107788	10441.3	652.579	0.02	0.00127841	0.000806185	12	3	10	10	126	76	0.641597	  nan	-2.12623	-0.641597	0	0	13748.8	859.301	0	0	0.000145432	0.000113509	 
diff --git a/...nc_multiclock/iterative/config/config.txt → ...nc_multiclock/iterative/config/config.txt b/...nc_multiclock/iterative/config/config.txt → ...nc_multiclock/iterative/config/config.txt
diff --git a/...s/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt b/...s/regression_tests/vtr_reg_multiclock/func_multiclock/iterative/config/golden_results.txt
@@ -0,0 +1,4 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  error	  odin_synth_time	  max_odin_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_time	  placed_wirelength_est	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	0.32	  	0.01	6736	1	0.02	-1	-1	35432	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	350784	6	1	13	14	2	8	9	4	4	16	  clb	  auto	0	13	0	0	0.875884	-3.21829	-0.875884	0.545	0.01	9.133E-06	6.332E-06	0.00137103	0.000893379	20	13	2	107788	107788	10441.3	652.579	0.02	0.00202846	0.00140832	13	11	27	27	298	166	1.17974	0.545	-3.80732	-1.17974	0	0	13748.8	859.301	0	0	0.000363437	0.000297087	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	0.44	  	0.02	7156	1	0.02	-1	-1	35752	-1	-1	2	3	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	353248	3	1	23	24	2	8	6	4	4	16	  clb	  auto	0.01	16	0	0	0.571	-8.02416	-0.571	0.557849	0.01	2.6392E-05	1.8474E-05	0.000392837	0.000356428	20	21	4	107788	107788	10441.3	652.579	0.02	0.00161969	0.00141089	14	2	7	7	87	53	0.639606	0.557849	-8.29417	-0.639606	0	0	13748.8	859.301	0	0	0.000617072	0.000570262	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	0.29	  	0.01	6724	1	0.01	-1	-1	33208	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	347368	6	2	10	12	2	8	10	4	4	16	  clb	  auto	0	12	0	0	0.543757	-1.83465	-0.543757	  nan	0.01	9.515E-06	6.506E-06	0.000866896	0.000551504	20	16	8	107788	107788	10441.3	652.579	0.02	0.00144256	0.000972468	21	4	13	13	358	237	0.81248	  nan	-2.64176	-0.81248	0	0	13748.8	859.301	0	0	0.000169618	0.000131886	 
diff --git a/...ticlock/multiclock_mcnc/config/config.txt → ...ticlock/multiclock_mcnc/config/config.txt b/...ticlock/multiclock_mcnc/config/config.txt → ...ticlock/multiclock_mcnc/config/config.txt
diff --git a/...multiclock_mcnc/config/golden_results.txt → ...multiclock_mcnc/config/golden_results.txt b/...multiclock_mcnc/config/golden_results.txt → ...multiclock_mcnc/config/golden_results.txt
diff --git a/...t2/func_multiclock/once/config/config.txt → ...ck/func_multiclock/once/config/config.txt b/...t2/func_multiclock/once/config/config.txt → ...ck/func_multiclock/once/config/config.txt
diff --git a/.../tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt b/.../tasks/regression_tests/vtr_reg_multiclock/func_multiclock/once/config/golden_results.txt
@@ -0,0 +1,4 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  error	  odin_synth_time	  max_odin_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_time	  placed_wirelength_est	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	0.26	  	0.01	6816	1	0.02	-1	-1	35772	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	349496	6	1	13	14	2	8	9	4	4	16	  clb	  auto	0	13	0	0	0.875884	-3.21829	-0.875884	0.545	0.01	9.091E-06	6.295E-06	0.00129808	0.000845104	20	13	2	107788	107788	10441.3	652.579	0.02	0.00198582	0.00138501	13	11	27	27	298	166	1.17974	0.545	-3.80732	-1.17974	0	0	13748.8	859.301	0	0	0.000358376	0.000292334	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	0.38	  	0.02	7200	1	0.02	-1	-1	35364	-1	-1	2	3	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	349496	3	1	25	26	2	8	6	4	4	16	  clb	  auto	0.01	16	0	0	0.571	-8.56916	-0.571	0.557849	0.01	2.6353E-05	1.8731E-05	0.000276021	0.00024129	20	21	4	107788	107788	10441.3	652.579	0.02	0.00149985	0.00130224	14	2	7	7	87	53	0.639606	0.557849	-8.83917	-0.639606	0	0	13748.8	859.301	0	0	0.000678691	0.000630364	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	0.28	  	0.01	6604	1	0.01	-1	-1	33600	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	352016	6	2	10	12	2	8	10	4	4	16	  clb	  auto	0	12	0	0	0.543757	-1.83465	-0.543757	  nan	0.01	1.3298E-05	9.555E-06	0.00112792	0.000716874	20	15	6	107788	107788	10441.3	652.579	0.02	0.00174703	0.00117687	12	3	10	10	126	76	0.641597	  nan	-2.12623	-0.641597	0	0	13748.8	859.301	0	0	0.00014824	0.000115483	 
diff --git a/...func_multiclock/vanilla/config/config.txt → ...func_multiclock/vanilla/config/config.txt b/...func_multiclock/vanilla/config/config.txt → ...func_multiclock/vanilla/config/config.txt
diff --git a/...sks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt b/...sks/regression_tests/vtr_reg_multiclock/func_multiclock/vanilla/config/golden_results.txt
@@ -0,0 +1,4 @@
+ arch	  circuit	  script_params	  vtr_flow_elapsed_time	  error	  odin_synth_time	  max_odin_mem	  abc_depth	  abc_synth_time	  abc_cec_time	  abc_sec_time	  max_abc_mem	  ace_time	  max_ace_mem	  num_clb	  num_io	  num_memories	  num_mult	  vpr_status	  vpr_revision	  vpr_build_info	  vpr_compiler	  vpr_compiled	  hostname	  rundir	  max_vpr_mem	  num_primary_inputs	  num_primary_outputs	  num_pre_packed_nets	  num_pre_packed_blocks	  num_netlist_clocks	  num_post_packed_nets	  num_post_packed_blocks	  device_width	  device_height	  device_grid_tiles	  device_limiting_resources	  device_name	  pack_time	  placed_wirelength_est	  place_time	  place_quench_time	  placed_CPD_est	  placed_setup_TNS_est	  placed_setup_WNS_est	  placed_geomean_nonvirtual_intradomain_critical_path_delay_est	  place_delay_matrix_lookup_time	  place_quench_timing_analysis_time	  place_quench_sta_time	  place_total_timing_analysis_time	  place_total_sta_time	  min_chan_width	  routed_wirelength	  min_chan_width_route_success_iteration	  logic_block_area_total	  logic_block_area_used	  min_chan_width_routing_area_total	  min_chan_width_routing_area_per_tile	  min_chan_width_route_time	  min_chan_width_total_timing_analysis_time	  min_chan_width_total_sta_time	  crit_path_routed_wirelength	  crit_path_route_success_iteration	  crit_path_total_nets_routed	  crit_path_total_connections_routed	  crit_path_total_heap_pushes	  crit_path_total_heap_pops	  critical_path_delay	  geomean_nonvirtual_intradomain_critical_path_delay	  setup_TNS	  setup_WNS	  hold_TNS	  hold_WNS	  crit_path_routing_area_total	  crit_path_routing_area_per_tile	  router_lookahead_computation_time	  crit_path_route_time	  crit_path_total_timing_analysis_time	  crit_path_total_sta_time	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_output_and_latch.v	  common	0.31	  	0.01	6784	1	0.02	-1	-1	35732	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	350952	6	1	13	14	2	8	9	4	4	16	  clb	  auto	0	13	0	0	0.875884	-3.21829	-0.875884	0.545	0.01	9.095E-06	6.307E-06	0.00129288	0.000842011	20	13	2	107788	107788	10441.3	652.579	0.02	0.00191938	0.00132537	13	11	27	27	298	166	1.17974	0.545	-3.80732	-1.17974	0	0	13748.8	859.301	0	0	0.000353606	0.000288916	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_reader_writer.v	  common	0.44	  	0.02	7184	1	0.02	-1	-1	35612	-1	-1	2	3	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	350112	3	1	23	24	2	8	6	4	4	16	  clb	  auto	0.01	16	0	0	0.571	-8.02416	-0.571	0.557849	0.01	2.6001E-05	1.8594E-05	0.000265426	0.000230778	20	21	4	107788	107788	10441.3	652.579	0.02	0.00142645	0.00123292	14	2	7	7	87	53	0.639606	0.557849	-8.29417	-0.639606	0	0	13748.8	859.301	0	0	0.000632038	0.000584601	 
+ k6_frac_N10_mem32K_40nm.xml	  multiclock_separate_and_latch.v	  common	0.28	  	0.01	6560	1	0.01	-1	-1	33160	-1	-1	2	6	0	0	  success	  v8.0.0-3544-g00617ff76	  Release VTR_ASSERT_LEVEL=2	  GNU 9.3.0 on Linux-5.8.0-53-generic x86_64	  2021-05-24T22:53:36	  CASA44	  /home/casauser/Desktop/Repos/sdamghan	351176	6	2	10	12	2	8	10	4	4	16	  clb	  auto	0	12	0	0	0.543757	-1.83465	-0.543757	  nan	0.01	7.409E-06	4.867E-06	0.000791344	0.000475707	20	16	8	107788	107788	10441.3	652.579	0.02	0.00133053	0.000866155	21	4	13	13	358	237	0.81248	  nan	-2.64176	-0.81248	0	0	13748.8	859.301	0	0	0.000176087	0.000137856	 
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_multiclock/task_list.txt
@@ -1,4 +1,4 @@
-regression_tests/vtr_reg_nightly_basic/func_multiclock/blanket
-regression_tests/vtr_reg_nightly_basic/func_multiclock/iterative
-regression_tests/vtr_reg_nightly_basic/func_multiclock/once
-regression_tests/vtr_reg_nightly_basic/func_multiclock/vanilla
+regression_tests/vtr_reg_multiclock/func_multiclock/blanket
+regression_tests/vtr_reg_multiclock/func_multiclock/iterative
+regression_tests/vtr_reg_multiclock/func_multiclock/once
+regression_tests/vtr_reg_multiclock/func_multiclock/vanilla
diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/task_list.txt
@@ -1,6 +1,7 @@
 #Refer to Issue #1770 for details. 
 #regression_tests/vtr_reg_nightly_test1/arithmetic_tasks/adder_trees
 
+regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc_equiv
 regression_tests/vtr_reg_nightly_test1/vpr_reg_mcnc
 regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_soft_logic_arch
 regression_tests/vtr_reg_nightly_test1/vtr_reg_fpu_hard_block_arch

diff --git a/...g_basic/regression_mcnc/config/config.txt → ...est1/vpr_reg_mcnc_equiv/config/config.txt b/...g_basic/regression_mcnc/config/config.txt → ...est1/vpr_reg_mcnc_equiv/config/config.txt
@@ -3,6 +3,9 @@
 # Configuration file for running experiments
 ##############################################
 
+#This task checks for logical equivalency of a netlist before and after VPR using ABC. It performs a formal equivalence check but tests the same 
+#benchmarks as vtr_reg_mcnc. 
+
 # Path to directory of circuits to use
 circuits_dir=benchmarks/blif/wiremap6
 
@@ -41,6 +44,8 @@ parse_file=vpr_standard.txt
 # Pass requirements
 pass_requirements_file=pass_requirements.txt
 
-#
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
 script_params=-starting_stage vpr --gen_post_synthesis_netlist on -check_equivalent --sweep_dangling_primary_ios off --sweep_constant_primary_outputs off --absorb_buffer_luts off 
 
diff --git a/...regression_mcnc/config/golden_results.txt → ..._reg_mcnc_equiv/config/golden_results.txt b/...regression_mcnc/config/golden_results.txt → ..._reg_mcnc_equiv/config/golden_results.txt
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		The tasks inside this directory tests that VTR can correctly handle multi-clock designs in different ways. The default way to handle multiple clocks is iterative.