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Modifications to the power estimation flow and documentation #1796

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Merged
merged 3 commits into from
Jul 16, 2021

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aman26kbm
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@aman26kbm aman26kbm commented Jul 7, 2021

Description

Some documentation changes for the power estimation flow.

  1. Fixing the heading hierarchy
  2. Changing function name from power_calc_primitive to power_usage_primitive
  3. Adding some clarity in the flow steps and what's the name of the output file.
  4. Adding example command of run_vtr_flow with -power enabled
  5. Adding that the power model doesn't model single-bit adders in logic blocks.

Also, a fix that was identified here: https://groups.google.com/g/vtr-users/c/7IzU83_amKs

Related Issue

#1797

Motivation and Context

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

1. Fixing the heading hierarchy
2. Changing function name from power_calc_primitive to power_usage_primitive
3. Adding some clarity in the flow steps and what's the name of the output file.
4. Adding example command of run_vtr_flow with -power enabled
5. Adding that the power model doesn't model single-bit adders in logic blocks.
@aman26kbm
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Filing an issue with the context and details for this. Will update in a bit.

@aman26kbm
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Filed an issue and linked it to this PR.

@aman26kbm aman26kbm requested review from jgoeders and vaughnbetz July 8, 2021 18:03
@aman26kbm
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I've pushed in the fix we discussed in https://groups.google.com/g/vtr-users/c/7IzU83_amKs to this PR.

@aman26kbm aman26kbm changed the title Modifications to the power estimation documentation Modifications to the power estimation flow and documentation Jul 15, 2021
@github-actions github-actions bot added the VPR VPR FPGA Placement & Routing Tool label Jul 15, 2021
@vaughnbetz
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Looks good to me; thanks @aman26kbm . @jgoeders : you are probably better able to review the detailed code update at the end of the code changes for correctness (it looks fine to me and is correctly going through all input ports; I don't know the power code well enough to say if all the calculations are correct but they all look reasonable).
The documentation changes and vtr_flow enhancements are very useful.
The yosys+odinII test isn't fully functional yet, so that's an expected failure. Will merge after the other tests pass if Jeff has no feedback or concerns.

@vaughnbetz vaughnbetz merged commit c06800f into verilog-to-routing:master Jul 16, 2021
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2 participants