Skip to content

Add missing includes. #1604

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Dec 14, 2020

Conversation

hzeller
Copy link
Contributor

@hzeller hzeller commented Dec 4, 2020

  • All new and existing tests passed

Signed-off-by: Henner Zeller <[email protected]>
@github-actions github-actions bot added the VPR VPR FPGA Placement & Routing Tool label Dec 4, 2020
@mithro
Copy link
Contributor

mithro commented Dec 4, 2020

@hzeller - Any idea if this could be automatically checked by icwyu or similar tool?

@hzeller
Copy link
Contributor Author

hzeller commented Dec 4, 2020

Yes, iwyu should be able to catch these things early. I suspect that it shouldn't be too hard to have it part of the CI-systems.

@vaughnbetz
Copy link
Contributor

Looks like everything passed except travis (which is almost certainly a travis issue).

@vaughnbetz vaughnbetz merged commit de52413 into verilog-to-routing:master Dec 14, 2020
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
VPR VPR FPGA Placement & Routing Tool
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants