Skip to content

Adding a TPU-like design to the VTR benchmark suite #1573

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Nov 8, 2020
Merged

Adding a TPU-like design to the VTR benchmark suite #1573

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
cf16710
Adding new benchmark (TPU) to documentation
aman26kbm Oct 14, 2020
9216935
Adding two TPU-like designs as benchmarks. They can be used for ML be…
aman26kbm Oct 13, 2020
0a66ee5
Odin: regenerate expectations
jeanlego Oct 18, 2020
c115a00
Merge pull request #3 from jeanlego/vtr_benchmark_tpu
aman26kbm Oct 18, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
71 changes: 71 additions & 0 deletions ODIN_II/regression_test/benchmark/task/large/synthesis_result.json
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1161,6 +1161,77 @@
"Longest Path": 2,
"Average Path": 2
},
"large/tpu.16x16.int8/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "large/tpu.16x16.int8/k6_frac_N10_frac_chain_mem32K_40nm",
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
"verilog": "tpu.16x16.int8.v",
"warnings": [
"tpu.16x16.int8.v:2298:7 [AST] Odin does not handle signed REG (counter)"
],
"max_rss(MiB)": 241.4,
"exec_time(ms)": 2140.9,
"synthesis_time(ms)": 2135.1,
"Latch Drivers": 1,
"Pi": 354,
"Po": 289,
"logic element": 59049,
"latch": 22362,
"Adder": 4988,
"Multiplier": 288,
"Memory": 256,
"generic logic size": 4,
"Longest Path": 1596,
"Average Path": 4,
"Estimated LUTs": 70497,
"Total Node": 86944
},
"large/tpu.32x32.int8/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "large/tpu.32x32.int8/k6_frac_N10_frac_chain_mem32K_40nm",
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
"verilog": "tpu.32x32.int8.v",
"warnings": [
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[0] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[1] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[2] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[3] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[4] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[5] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[6] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:1569:18 [NETLIST] This module port final_mat_mul_size[7] is unused in module systolic_data_setup",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[0] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[1] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[2] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[3] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[4] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[5] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[6] is unused in module output_logic",
"tpu.32x32.int8.v:2881:18 [NETLIST] This module port final_mat_mul_size[7] is unused in module output_logic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[0] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[1] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[2] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[3] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[4] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[5] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[6] is unused in module matmul_32x32_systolic",
"tpu.32x32.int8.v:15361:1 [NETLIST] This module port (null)[7] is unused in module matmul_32x32_systolic"
],
"max_rss(MiB)": 811.1,
"exec_time(ms)": 8389.9,
"synthesis_time(ms)": 8384.1,
"Latch Drivers": 1,
"Pi": 642,
"Po": 545,
"logic element": 190121,
"latch": 85146,
"Adder": 18297,
"Multiplier": 1088,
"Memory": 512,
"generic logic size": 4,
"Longest Path": 3164,
"Average Path": 4,
"Estimated LUTs": 209209,
"Total Node": 295165
},
"DEFAULT": {
"test_name": "n/a",
"architecture": "n/a",
Expand Down
2 changes: 2 additions & 0 deletions doc/src/vtr/benchmarks.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,8 @@ They are suitable for FPGA architecture research and medium-scale CAD research.
stereovision1 Computer Vision
stereovision2 Computer Vision
stereovision3 Computer Vision
tpu.32x32.int8 Deep Learning
tpu.16x16.int8 Deep Learning
================ =================

The VTR benchmarks are provided as Verilog under: ::
Expand Down
Loading