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Odin: fix memory leak in c simple print function #1393

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Merged
merged 1 commit into from
Jul 4, 2020
Merged

Odin: fix memory leak in c simple print function #1393

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61 changes: 37 additions & 24 deletions ODIN_II/SRC/ast_util.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1338,39 +1338,52 @@ void assert_constant_positionnal_args(ast_node_t* node, long arg_count) {
* a simple printf would not be able to do this since escaped characters are compile time
*/
void c_simple_print(std::string str) {
size_t str_size = str.size();
size_t start = 0;
while (start != std::string::npos) {
size_t format_char_index = str.find_first_of('\\', start);
size_t next_char = format_char_index;
printf("%s", str.substr(start, format_char_index).c_str());
if (start != format_char_index) {
printf("%s", str.substr(start, format_char_index).c_str());
}
// print the string
if (format_char_index != std::string::npos) {
// try and see if its an octal number
char buffer[4] = {
str[format_char_index + 1],
str[format_char_index + 2],
str[format_char_index + 3],
0};
next_char = format_char_index + 4;
char* endptr = NULL;
char octal_value = (char)strtoul(buffer, &endptr, 8);
if (endptr == &buffer[3]) {
// if it is an octal number print the octal char
printf("%c", octal_value);
} else {
next_char = format_char_index + 2;
switch (str[format_char_index + 1]) {
case 'n':
printf("\n");
break;
case 't':
printf("\t");
break;
default:
next_char = format_char_index + 2;
switch (str[format_char_index + 1]) {
case 'n':
printf("\n");
break;
case 't':
printf("\t");
break;
default:
// can only be octal if there is 3+ chars following
if ((str_size - 3) >= format_char_index) {
// try and see if its an octal number
char buffer[4] = {
str[format_char_index + 1],
str[format_char_index + 2],
str[format_char_index + 3],
0};
next_char = format_char_index + 4;
char* endptr = NULL;
char octal_value = (char)strtoul(buffer, &endptr, 8);
if (endptr == &buffer[3]) {
// if it is an octal number print the octal char
printf("%c", octal_value);
} else {
// otherwise just print the character
next_char = format_char_index + 2;
printf("%c", str[format_char_index + 1]);
break;
}

} else {
// otherwise just print the character
next_char = format_char_index + 2;
printf("%c", str[format_char_index + 1]);
break;
}
}
}
}
start = next_char;
Expand Down
122 changes: 122 additions & 0 deletions ODIN_II/regression_test/benchmark/task/test/simulation_result.json
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Original file line number Diff line number Diff line change
@@ -0,0 +1,122 @@
{
"test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm",
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
"blif": "ifdef_undefined.blif",
"exit": 134,
"errors": [
"OUTPUT_BLIF Vector files differ."
],
"warnings": [
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
],
"max_rss(MiB)": -1,
"exec_time(ms)": -1,
"simulation_time(ms)": -1,
"test_coverage(%)": -1,
"Latch Drivers": -1,
"Pi": -1,
"Po": -1,
"logic element": -1,
"latch": -1,
"Adder": -1,
"Multiplier": -1,
"Memory": -1,
"Hard Ip": -1,
"generic logic size": 4,
"Longest Path": -1,
"Average Path": -1,
"Estimated LUTs": -1,
"Total Node": -1
},
"test/ifdef_undefined/k6_N10_40nm": {
"test_name": "test/ifdef_undefined/k6_N10_40nm",
"architecture": "k6_N10_40nm.xml",
"blif": "ifdef_undefined.blif",
"exit": 134,
"errors": [
"OUTPUT_BLIF Vector files differ."
],
"warnings": [
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
],
"max_rss(MiB)": -1,
"exec_time(ms)": -1,
"simulation_time(ms)": -1,
"test_coverage(%)": -1,
"Latch Drivers": -1,
"Pi": -1,
"Po": -1,
"logic element": -1,
"latch": -1,
"Adder": -1,
"Multiplier": -1,
"Memory": -1,
"Hard Ip": -1,
"generic logic size": 6,
"Longest Path": -1,
"Average Path": -1,
"Estimated LUTs": -1,
"Total Node": -1
},
"test/ifdef_undefined/k6_N10_mem32K_40nm": {
"test_name": "test/ifdef_undefined/k6_N10_mem32K_40nm",
"architecture": "k6_N10_mem32K_40nm.xml",
"blif": "ifdef_undefined.blif",
"exit": 134,
"errors": [
"OUTPUT_BLIF Vector files differ."
],
"warnings": [
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
],
"max_rss(MiB)": -1,
"exec_time(ms)": -1,
"simulation_time(ms)": -1,
"test_coverage(%)": -1,
"Latch Drivers": -1,
"Pi": -1,
"Po": -1,
"logic element": -1,
"latch": -1,
"Adder": -1,
"Multiplier": -1,
"Memory": -1,
"Hard Ip": -1,
"generic logic size": 6,
"Longest Path": -1,
"Average Path": -1,
"Estimated LUTs": -1,
"Total Node": -1
},
"test/ifdef_undefined/no_arch": {
"test_name": "test/ifdef_undefined/no_arch",
"architecture": "n/a",
"blif": "ifdef_undefined.blif",
"exit": 134,
"errors": [
"OUTPUT_BLIF Vector files differ."
],
"warnings": [
"OUTPUT_BLIF Simulation produced fewer than 2 vectors."
],
"max_rss(MiB)": -1,
"exec_time(ms)": -1,
"simulation_time(ms)": -1,
"test_coverage(%)": -1,
"Latch Drivers": -1,
"Pi": -1,
"Po": -1,
"logic element": -1,
"latch": -1,
"Adder": -1,
"Multiplier": -1,
"Memory": -1,
"Hard Ip": -1,
"generic logic size": -1,
"Longest Path": -1,
"Average Path": -1,
"Estimated LUTs": -1,
"Total Node": -1
}
}
118 changes: 118 additions & 0 deletions ODIN_II/regression_test/benchmark/task/test/synthesis_result.json
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Original file line number Diff line number Diff line change
@@ -0,0 +1,118 @@
{
"test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm": {
"test_name": "test/ifdef_undefined/k6_frac_N10_frac_chain_mem32K_40nm",
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
"verilog": "ifdef_undefined.v",
"exit": 0,
"errors": [],
"warnings": [
"OUTPUT_BLIF want to see if this will print json",
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
],
"max_rss(MiB)": 32.8,
"exec_time(ms)": 71.3,
"synthesis_time(ms)": 0.7,
"Latch Drivers": 0,
"Pi": 0,
"Po": 1,
"logic element": 0,
"latch": 0,
"Adder": 0,
"Multiplier": 0,
"Memory": 0,
"Hard Ip": -1,
"generic logic size": 4,
"Longest Path": 1,
"Average Path": 1,
"Estimated LUTs": 0,
"Total Node": 0
},
"test/ifdef_undefined/k6_N10_40nm": {
"test_name": "test/ifdef_undefined/k6_N10_40nm",
"architecture": "k6_N10_40nm.xml",
"verilog": "ifdef_undefined.v",
"exit": 0,
"errors": [],
"warnings": [
"OUTPUT_BLIF want to see if this will print json",
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
],
"max_rss(MiB)": 15.1,
"exec_time(ms)": 11,
"synthesis_time(ms)": 0.9,
"Latch Drivers": 0,
"Pi": 0,
"Po": 1,
"logic element": 0,
"latch": 0,
"Adder": -1,
"Multiplier": -1,
"Memory": -1,
"Hard Ip": -1,
"generic logic size": 6,
"Longest Path": 1,
"Average Path": 1,
"Estimated LUTs": 0,
"Total Node": 0
},
"test/ifdef_undefined/k6_N10_mem32K_40nm": {
"test_name": "test/ifdef_undefined/k6_N10_mem32K_40nm",
"architecture": "k6_N10_mem32K_40nm.xml",
"verilog": "ifdef_undefined.v",
"exit": 0,
"errors": [],
"warnings": [
"OUTPUT_BLIF want to see if this will print json",
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
],
"max_rss(MiB)": 32.2,
"exec_time(ms)": 51.1,
"synthesis_time(ms)": 0.5,
"Latch Drivers": 0,
"Pi": 0,
"Po": 1,
"logic element": 0,
"latch": 0,
"Adder": -1,
"Multiplier": 0,
"Memory": 0,
"Hard Ip": -1,
"generic logic size": 6,
"Longest Path": 1,
"Average Path": 1,
"Estimated LUTs": 0,
"Total Node": 0
},
"test/ifdef_undefined/no_arch": {
"test_name": "test/ifdef_undefined/no_arch",
"architecture": "n/a",
"verilog": "ifdef_undefined.v",
"exit": 0,
"errors": [],
"warnings": [
"OUTPUT_BLIF want to see if this will print json",
"NETLIST ifdef_undefined.v:5 This output is undriven (simple_op^out) and will be removed",
"NETLIST Net simple_op^out driving node simple_op^out is itself undriven."
],
"max_rss(MiB)": 11.1,
"exec_time(ms)": 4.6,
"synthesis_time(ms)": 1.8,
"Latch Drivers": 0,
"Pi": 0,
"Po": 1,
"logic element": 0,
"latch": 0,
"Adder": -1,
"Multiplier": -1,
"Memory": -1,
"Hard Ip": -1,
"generic logic size": -1,
"Longest Path": 1,
"Average Path": 1,
"Estimated LUTs": 0,
"Total Node": 0
}
}
23 changes: 23 additions & 0 deletions ODIN_II/regression_test/benchmark/task/test/task.conf
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########################
# operators benchmarks config
########################

regression_params=--include_default_arch
script_synthesis_params=--time_limit 3600s
script_simulation_params=--time_limit 3600s
simulation_params= -L reset rst -H we

# setup the architecture
archs_dir=../vtr_flow/arch/timing

arch_list_add=k6_N10_40nm.xml
arch_list_add=k6_N10_mem32K_40nm.xml
arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

# setup the circuits
circuits_dir=regression_test/benchmark/verilog/

circuit_list_add=test/*.v

synthesis_parse_file=regression_test/parse_result/conf/synth.toml
simulation_parse_file=regression_test/parse_result/conf/sim.toml
2 changes: 1 addition & 1 deletion ODIN_II/regression_test/benchmark/verilog/FIR/ex1BT16_fir_20_input
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Original file line number Diff line number Diff line change
Expand Up @@ -395,4 +395,4 @@ GLOBAL_SIM_BASE_CLK clk In_X
0 1 0X227
1 0 0X826
0 0 0X255
1 1 0X114
1 1 0X114
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