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Nov 8, 2020
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1f39653
add post routing cluster block pin fix-up
tangxifan Jun 10, 2020
ee7b26c
for code format fix
tangxifan Jun 10, 2020
c417e68
streamline the code: rename functions, add comments and remove rr_nod…
tangxifan Jun 11, 2020
f161dd7
bug fix in pb_pin_fixup on the grid walk through
tangxifan Jun 11, 2020
95ed026
bug fix in fix-up
tangxifan Jun 12, 2020
f13f432
apply modification on pb_route but break timing analyzer; debugging now
tangxifan Jun 18, 2020
069774c
many bug fix in pb route synchornization; passed most regression test…
tangxifan Jul 8, 2020
004b704
code format fix
tangxifan Jul 8, 2020
dcf6acd
try to fix the bug for stratix4 arch but found fatal error in the arc…
tangxifan Jul 8, 2020
135b063
code format fix and comment out debugging print out
tangxifan Jul 8, 2020
dd91dac
ensure clean start for net remapping data structure; correcting fasm …
tangxifan Jul 8, 2020
0313fb3
ensure a clean start for clustered netlist annotation when loading pa…
tangxifan Jul 8, 2020
b55a414
turn off verbose output of fix up function
tangxifan Jul 9, 2020
b9b61e5
compact codes using quick searches based on cluster blocks
tangxifan Jul 10, 2020
06bab4c
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
tangxifan Sep 17, 2020
7383aad
[VPR] relax the checking codes due to the rr_graph fix-up
tangxifan Sep 17, 2020
081158d
[VPR] code format fix
tangxifan Sep 17, 2020
5620ed8
[VPR] code format fix
tangxifan Sep 17, 2020
220f0b3
[VPR] code streamline
tangxifan Oct 4, 2020
dfcd29d
[VPR] Remove redundant codes
tangxifan Oct 4, 2020
ea6a1e2
[VPR] Bug fix due to code cleanup
tangxifan Oct 5, 2020
9476080
[Flow] Add test cases for post routing synchronization
tangxifan Oct 5, 2020
dc82fd1
[Flow] Add the post-routing sync test case to strong regression tests
tangxifan Oct 5, 2020
82c1743
[Flow] Add Lattic-style architecture without local routing to validat…
tangxifan Oct 5, 2020
924e5cd
[Flow] Debugging the strong test case for non LR architecture
tangxifan Oct 5, 2020
01ffcfb
[VPR] Add more debugging information in timing analyzer
tangxifan Oct 5, 2020
fff5833
[VPR] Now the post-routing fix-up works for false equivalent pins
tangxifan Oct 8, 2020
00c5dbc
[VPR] code format fix
tangxifan Oct 8, 2020
e05c862
[VPR] Add a mutable method to find pb in t_pb data structure
tangxifan Oct 8, 2020
10bee17
[VPR] Bug fix due to aggressive caching the atom pins during post rou…
tangxifan Oct 8, 2020
7646a3e
[VPR] Turn off verbose output
tangxifan Oct 8, 2020
40f75f1
[Flow] Add more benchmarks to the test case for post-routing synchron…
tangxifan Oct 8, 2020
b151476
[Flow] Add golden results for post-routing sync test case
tangxifan Oct 8, 2020
1468c99
[VPR] Remove debugging codes
tangxifan Oct 8, 2020
6a54adb
[VPR] Add statistics to post routing fix-up
tangxifan Oct 10, 2020
ea7acf1
[VPR] Move post-routing fix-up to analysis flow
tangxifan Oct 20, 2020
ecfe373
[VPR] Add packing results XML writer API and call it at the end of fi…
tangxifan Oct 20, 2020
aa33814
[VPR] code format fix
tangxifan Oct 21, 2020
6d2da58
[Doc] Update documentation with explanation on .net files
tangxifan Oct 22, 2020
6fda4fc
[Doc] Update with more clarification on the .net file usage
tangxifan Oct 27, 2020
89d927a
[Doc] Add more explanation on the usage of post-routing .net file
tangxifan Oct 27, 2020
f7f68d4
[VPR] Now flag fatal error in netlist writer when nets do not match
tangxifan Oct 27, 2020
360edcd
[VPR] Now verbose output of post-routing pb pin fix-up API can be ena…
tangxifan Oct 27, 2020
8ddc594
[VPR] Update routing net annotation with more sanity checks
tangxifan Oct 27, 2020
ef4491d
[VPR] Avoid string building in delay calualtor when assertation holds
tangxifan Oct 27, 2020
75246db
[VPR] Remove commented codes in pb pin fix-up API
tangxifan Oct 27, 2020
a604597
[Doc] Typo fix
tangxifan Oct 27, 2020
e0ce4b1
[Doc] Add warning to clarify the limitation of current fix-up
tangxifan Oct 27, 2020
277ff48
[VPR] bug fix for routing net annotation due to rr_node capacity > 1
tangxifan Oct 27, 2020
5467fc3
[VPR] code format fix
tangxifan Oct 27, 2020
95e704a
[VPR] code format fix
tangxifan Oct 27, 2020
62335b5
[VPR] Rename the overloaded get_physical_pin() function to get_post_p…
tangxifan Nov 3, 2020
7296b32
[VPR] Now consider the max. number of pins among equivalent sites whe…
tangxifan Nov 3, 2020
88124ff
[VPR] code format fix
tangxifan Nov 4, 2020
0aca71d
[VPR] Code format fix
tangxifan Nov 4, 2020
e02b3d2
[VPR] Use standard API to get the number of pins per block in a subtile
tangxifan Nov 4, 2020
801848d
[VPR] Add comments for the overloaded API
tangxifan Nov 4, 2020
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8 changes: 8 additions & 0 deletions doc/src/vpr/file_formats.rst
Original file line number Diff line number Diff line change
Expand Up @@ -585,6 +585,14 @@ The io pad is set to inpad mode and is driven by the inpad:
</block>
...

.. note:: ``.net`` files may be outputted at two stages:
- After packing is completed, the packing results will be outputted. The ``.net`` file can be loaded as an input for placer, router and analyzer. Note that the file may **not** represent the final packing results as the analyzer will apply synchronization between packing and routing results.
- After analysis is completed, updated packing results will be outputted. This is due to that VPR router may swap pin mapping in packing results for optimizations. In such cases, packing results are synchronized with routing results. The outputted ``.net`` file will have a postfix of ``.post_routing`` as compared to the original packing results. It could happen that VPR router does not apply any pin swapping and the two ``.net`` files are the same. In both cases, the post-analysis ``.net`` file should be considered to be **the final packing results** for downstream tools, e.g., bitstream generator. Users may load the post-routing ``.net`` file in VPR's analysis flow to sign-off the final results.

.. warning:: Currently, the packing result synchronization is only applicable to input pins which may be remapped to different nets during routing optimization. If your architecture defines `link_instance_pin_xml_syntax_` equivalence for output pins, the packing results still mismatch the routing results!

.. _link_instance_pin_xml_syntax: https://docs.verilogtorouting.org/en/latest/arch/reference/#tag-%3Coutputname=

.. _vpr_place_file:

Placement File Format (.place)
Expand Down
12 changes: 11 additions & 1 deletion vpr/src/base/netlist_writer.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1818,7 +1818,17 @@ class NetlistWriterVisitor : public NetlistVisitor {
if (impl_input_net_id) {
//If there is a valid net connected in the implementation
AtomNetId logical_net_id = atom_ctx.nlist.port_net(port_id, orig_index);
VTR_ASSERT(impl_input_net_id == logical_net_id);

// Fatal error should be flagged when the net marked in implementation
// does not match the net marked in input netlist
if (impl_input_net_id != logical_net_id) {
VPR_FATAL_ERROR(VPR_ERROR_IMPL_NETLIST_WRITER,
"Unmatch:\n\tlogical net is '%s' at pin '%lu'\n\timplmented net is '%s' at pin '%s'\n",
atom_ctx.nlist.net_name(logical_net_id).c_str(),
size_t(orig_index),
atom_ctx.nlist.net_name(impl_input_net_id).c_str(),
gpin->to_string().c_str());
}

//Mark the permutation.
// The net originally located at orig_index in the atom netlist
Expand Down
33 changes: 31 additions & 2 deletions vpr/src/base/vpr_api.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@
#include "constant_nets.h"
#include "atom_netlist_utils.h"
#include "cluster.h"
#include "output_clustering.h"

#include "pack_report.h"
#include "overuse_report.h"
Expand All @@ -81,6 +82,8 @@

#include "arch_util.h"

#include "post_routing_pb_pin_fixup.h"

#include "log.h"
#include "iostream"

Expand Down Expand Up @@ -587,6 +590,10 @@ void vpr_load_packing(t_vpr_setup& vpr_setup, const t_arch& arch) {

auto& cluster_ctx = g_vpr_ctx.mutable_clustering();

/* Ensure we have a clean start with void net remapping information */
cluster_ctx.post_routing_clb_pin_nets.clear();
cluster_ctx.pre_routing_net_pin_mapping.clear();

cluster_ctx.clb_nlist = read_netlist(vpr_setup.FileNameOpts.NetFile.c_str(),
&arch,
vpr_setup.FileNameOpts.verify_file_digests,
Expand Down Expand Up @@ -743,8 +750,6 @@ RouteStatus vpr_route_flow(t_vpr_setup& vpr_setup, const t_arch& arch) {
}
}

VTR_LOG("\n");

//Echo files
if (vpr_setup.Timing.timing_analysis_enabled) {
if (isEchoFileEnabled(E_ECHO_FINAL_ROUTING_TIMING_GRAPH)) {
Expand Down Expand Up @@ -1183,6 +1188,30 @@ bool vpr_analysis_flow(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteSt
VTR_LOG("*****************************************************************************************\n");
}

/* If routing is successful, apply post-routing annotations
* - apply logic block pin fix-up
*
* Note:
* - Turn on verbose output when users require verbose output
* for packer (default verbosity is set to 2 for compact logs)
*/
if (route_status.success()) {
sync_netlists_to_routing(g_vpr_ctx.device(),
g_vpr_ctx.mutable_atom(),
g_vpr_ctx.mutable_clustering(),
g_vpr_ctx.placement(),
g_vpr_ctx.routing(),
vpr_setup.PackerOpts.pack_verbosity > 2);

std::string post_routing_packing_output_file_name = vpr_setup.PackerOpts.output_file + ".post_routing";
write_packing_results_to_xml(vpr_setup.PackerOpts.global_clocks,
Arch.architecture_id,
post_routing_packing_output_file_name.c_str());
} else {
VTR_LOG_WARN("Sychronization between packing and routing results is not applied due to illegal circuit implementation\n");
}
VTR_LOG("\n");

vpr_analysis(vpr_setup, Arch, route_status);

return true;
Expand Down
10 changes: 10 additions & 0 deletions vpr/src/base/vpr_context.h
Original file line number Diff line number Diff line change
Expand Up @@ -268,6 +268,16 @@ struct ClusteringContext : public Context {

///@brief New netlist class derived from Netlist
ClusteredNetlist clb_nlist;

/* Database for nets of each clb block pin after routing stage
* - post_routing_clb_pin_nets:
* mapping of pb_type pins to clustered net ids
* - pre_routing_net_pin_mapping:
* a copy of mapping for current pb_route index to previous pb_route index
* Record the previous pin mapping for finding the correct pin index during timing analysis
*/
std::map<ClusterBlockId, std::map<int, ClusterNetId>> post_routing_clb_pin_nets;
std::map<ClusterBlockId, std::map<int, int>> pre_routing_net_pin_mapping;
};

/**
Expand Down
29 changes: 28 additions & 1 deletion vpr/src/base/vpr_types.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -70,7 +70,7 @@ t_mode* t_pb::get_mode() const {
}

/**
* @brief Returns the t_pb associated with the specified gnode which is contained
* @brief Returns the read-only t_pb associated with the specified gnode which is contained
* within the current pb
*/
const t_pb* t_pb::find_pb(const t_pb_graph_node* gnode) const {
Expand All @@ -96,6 +96,33 @@ const t_pb* t_pb::find_pb(const t_pb_graph_node* gnode) const {
return nullptr; //Not found
}

/**
* @brief Returns the mutable t_pb associated with the specified gnode which is contained
* within the current pb
*/
t_pb* t_pb::find_mutable_pb(const t_pb_graph_node* gnode) {
//Base case
if (pb_graph_node == gnode) {
return this;
}

//Search recursively
for (int ichild_type = 0; ichild_type < get_num_child_types(); ++ichild_type) {
if (child_pbs[ichild_type] == nullptr) continue;

for (int ipb = 0; ipb < get_num_children_of_type(ichild_type); ++ipb) {
t_pb* child_pb = &child_pbs[ichild_type][ipb];

t_pb* found_pb = child_pb->find_mutable_pb(gnode);
if (found_pb != nullptr) {
VTR_ASSERT(found_pb->pb_graph_node == gnode);
return found_pb; //Found
}
}
}
return nullptr; //Not found
}

const t_pb* t_pb::find_pb_for_model(const std::string& blif_model) const {
//Base case
const t_model* model = pb_graph_node->pb_type->model;
Expand Down
8 changes: 7 additions & 1 deletion vpr/src/base/vpr_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -325,11 +325,17 @@ class t_pb {
t_mode* get_mode() const;

/**
* @brief Returns the t_pb associated with the specified gnode which is contained
* @brief Returns the read-only t_pb associated with the specified gnode which is contained
* within the current pb
*/
const t_pb* find_pb(const t_pb_graph_node* gnode) const;

/**
* @brief Returns the mutable t_pb associated with the specified gnode which is contained
* within the current pb
*/
t_pb* find_mutable_pb(const t_pb_graph_node* gnode);

const t_pb* find_pb_for_model(const std::string& blif_model) const;

///@brief Returns the root pb containing this pb
Expand Down
24 changes: 24 additions & 0 deletions vpr/src/pack/output_clustering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,7 @@
#include "output_clustering.h"
#include "read_xml_arch_file.h"
#include "vpr_utils.h"
#include "pack.h"

#define LINELENGTH 1024
#define TAB_LENGTH 4
Expand Down Expand Up @@ -615,3 +616,26 @@ void output_clustering(const vtr::vector<ClusterBlockId, std::vector<t_intra_lb_
}
}
}

/********************************************************************
* An useful API to output packing results to a XML file
* This function is a wrapper for the function output_clustering()
* but remove all the requirements on input data structures that
* have to be built with other APIs
*
* As such, this function is expected to be a standard API
* which can be called anytime and anywhere after packing is finished.
********************************************************************/
void write_packing_results_to_xml(const bool& global_clocks,
const std::string& architecture_id,
const char* out_fname) {
vtr::vector<ClusterBlockId, std::vector<t_intra_lb_net>*> intra_lb_routing_placeholder;
std::unordered_set<AtomNetId> is_clock = alloc_and_load_is_clock(global_clocks);

output_clustering(intra_lb_routing_placeholder,
global_clocks,
is_clock,
architecture_id,
out_fname,
false);
}
2 changes: 2 additions & 0 deletions vpr/src/pack/output_clustering.h
Original file line number Diff line number Diff line change
Expand Up @@ -7,4 +7,6 @@

void output_clustering(const vtr::vector<ClusterBlockId, std::vector<t_intra_lb_net>*>& intra_lb_routing, bool global_clocks, const std::unordered_set<AtomNetId>& is_clock, const std::string& architecture_id, const char* out_fname, bool skip_clustering);

void write_packing_results_to_xml(const bool& global_clocks, const std::string& architecture_id, const char* out_fname);

#endif
1 change: 0 additions & 1 deletion vpr/src/pack/pack.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,6 @@
/* #define DUMP_PB_GRAPH 1 */
/* #define DUMP_BLIF_INPUT 1 */

static std::unordered_set<AtomNetId> alloc_and_load_is_clock(bool global_clocks);
static bool try_size_device_grid(const t_arch& arch, const std::map<t_logical_block_type_ptr, size_t>& num_type_instances, float target_device_utilization, std::string device_layout_name);

static t_ext_pin_util_targets parse_target_external_pin_util(std::vector<std::string> specs);
Expand Down
4 changes: 4 additions & 0 deletions vpr/src/pack/pack.h
Original file line number Diff line number Diff line change
@@ -1,7 +1,9 @@
#ifndef PACK_H
#define PACK_H
#include <vector>
#include <unordered_set>
#include "vpr_types.h"
#include "atom_netlist_fwd.h"

bool try_pack(t_packer_opts* packer_opts,
const t_analysis_opts* analysis_opts,
Expand All @@ -13,4 +15,6 @@ bool try_pack(t_packer_opts* packer_opts,

float get_arch_switch_info(short switch_index, int switch_fanin, float& Tdel_switch, float& R_switch, float& Cout_switch);

std::unordered_set<AtomNetId> alloc_and_load_is_clock(bool global_clocks);

#endif
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