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Compiler directives benchmarks #1331

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Merged
merged 6 commits into from
Jul 6, 2020
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emacdo12
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@emacdo12 emacdo12 commented Jun 2, 2020

Description

Created a section in regression tests for benchmarks that test compiler directives. Also, added to basic.toml an expectation tag that will describe if tests are meant to be passed and why they would fail. This will show in the json simulation file.

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Motivation and Context

Tests the functionality of compiler directives and reveals bugs.

How Has This Been Tested?

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code lang-hdl Hardware Description Language (Verilog/VHDL) Odin Odin II Logic Synthesis Tool: Unsorted item tests labels Jun 2, 2020
@jeanlego
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jeanlego commented Jun 3, 2020

it seems you added the Expected display but haven't regenerated all the expected results, travis Is currently failing because of this https://travis-ci.com/github/verilog-to-routing/vtr-verilog-to-routing/jobs/342806831. I would either consider dropping it for now or updating all of them. I like the idea and I do think it would be very usefull.

@jeanlego
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jeanlego commented Jul 3, 2020

Once Travis passes, it's ready to be merged

emacdo12 and others added 6 commits July 6, 2020 09:03
…ectives which can be found in the preprocessor file. Additionally, created an "expected" option for json files that allows us to identify benchmarks that should be passed but fail due to bugs or unsupported functions. This allows developers creating benchmarks

to go more in depth on why a test may be failing and possible solutions. All json files have been updated accordingly to include the expectation.
@jeanlego jeanlego merged commit c62dcaf into verilog-to-routing:master Jul 6, 2020
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2 participants