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Initial implementation of explicit ports. #1065

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This implements part one of #1063

@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code libarchfpga Library for handling FPGA Architecture descriptions tests VPR VPR FPGA Placement & Routing Tool VTR Flow VTR Design Flow (scripts/benchmarks/architectures) labels Dec 12, 2019
@litghost litghost force-pushed the proposed_explicit_ports branch from a72781e to 27e6b1e Compare December 12, 2019 08:54
@litghost litghost changed the title Implement initial explicit ports. Initial implemention explicit ports. Dec 12, 2019
@litghost litghost changed the title Initial implemention explicit ports. Initial implementation of explicit ports. Dec 12, 2019
@litghost litghost force-pushed the proposed_explicit_ports branch from 27e6b1e to 239b0f0 Compare December 12, 2019 17:09
@litghost litghost changed the title Initial implementation of explicit ports. WIP: Initial implementation of explicit ports. Dec 12, 2019
@litghost litghost mentioned this pull request Dec 13, 2019
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@litghost litghost force-pushed the proposed_explicit_ports branch from 239b0f0 to abb3f54 Compare December 13, 2019 22:12
@litghost litghost changed the title WIP: Initial implementation of explicit ports. Initial implementation of explicit ports. Dec 14, 2019
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@vaughnbetz @kmurray I know we talked about a different direction (e.g. stacks of physical tiles) but this change was significantly easier to implement in the short term, and unblocked progress on the Symbiflow front.

Take a look. Some of the changes here I think are better than the previous code (e.g. more robust / less assumptions), in particular I'm thinking about how the new code translates IPIN/OPIN rr nodes back to clusters. I can isolate those changes if you want to accept them.

I also think adding heterogeneous logical tiles is fairly straight-forward from this PR, where-as stacks of physical tiles is going to be a lot more work (e.g. code changes), but I agree with the reasoning why to take one approach over another. In the new year, I may finish the heterogeneous logical tiles before circling back and making the larger changes required to support stacks of physical tiles.

@litghost litghost closed this Mar 12, 2020
@litghost litghost deleted the proposed_explicit_ports branch March 12, 2020 03:45
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