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Support arithmetic right shift by constant value #415

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Scott-Young-6746 opened this issue Dec 4, 2018 · 1 comment
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Support arithmetic right shift by constant value #415

Scott-Young-6746 opened this issue Dec 4, 2018 · 1 comment

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@Scott-Young-6746
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Proposed Behaviour

for any input or intermediate vector or number a, constant C and output o the following verilog should compile and output the correct BLIF.
o = a >>> C;

Current Behaviour

Current behavior causes the ODIN II compiler to exit with an unsupported message.

Possible Solution

Context
@Scott-Young-6746 Scott-Young-6746 mentioned this issue Dec 4, 2018
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@jeanlego
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this issue is resolved with PR #416 416

litghost added a commit to litghost/vtr-verilog-to-routing that referenced this issue Mar 4, 2020
@litghost
Merge pull request verilog-to-routing#415 from litghost/merge_with_up…
efc87ec 
…stream

Merge with latest upstream VPR
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@Scott-Young-6746 @jeanlego