Needed features in VTR description to represent Xilinx architecture

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Proposed Behaviour

The following is a list of functionality that would need to be supported in VTR in order to obtain an approximate capture of the Xilinx architecture:

Core functionality

• Support for different distributions of wires in the vertical/horizontal.

  • Most of the functionality for this was brought in with PR Generalizing channels & segments to horizontal and vertical in rr_graph #1883 although porting the functionality to work with custom SB's remains as an action item.

• Support for non-uniform chanel widths

  • As above, PR Generalizing channels & segments to horizontal and vertical in rr_graph #1883 has allowed for this functionality but work still needs to be done with custom SBs.

• Support for the two points above for custom SB.

• Support for different shaped wires (diagonals/T shaped in particular).

  • PR Addition of switch_override feature to custom SB #2067 will make the necessary changes to allow for this feature although diagonal wires will need to be modeled through custom SB.

• In xilinx there are stubs, or jumps between SB (i.e. a wire terminates in two SB instead of one).

• Xilinx has several highly connected PIPJ's called bounce pips to which alternative pip's can connect.

• Xilinx has sets of wires that leave a connection block, enter an SB, and then bounce back into the same connection block (termed as a bounce pip in Xilinx). Although this is not technically supported by VTR the same affect can be modeled using internal crossbars.

Additional features

• Support for tile layouts beyond that currently supported by VTR.

  • Following the island style, VTR currently has a pattern of CB, Logic, CB, ...
  • Xilinx has a pattern of SB/CB, SB/CB, Logic, Logic, SB/CB, SB/CB, ... (see images in following post).

• Support for both bi-directional and uni-directional segments in the same arch. VTR currently only supports one or the other. This item is not too important since only the longest wire segments in the Xilinx arch are bi-directional (L12 and L18).

• Xilinx allows for all of its wires to make connections to wires traveling in the opposite direction of travel (i.e. any wire traveling south may connect to a wire of length one traveling north). VTR currently does not allow for this or at the very least it is not fully supported. This could prove important because it allows for wires to easily connect to LB that are an odd length away (i.e. an LB located west 3 units can be accessed by using WW4->E1).

• Xilinx multipliers have input widths that are not equal (25x18 vs. 32x32). This causes some packing issues on certain benchmarks that need to be fixed.

• In the Xilinx arch switch blocks and connection blocks are combined into one (improving space and routablitiy). The island style FPGA supported by VTR currently separates the two. This can be implemented by lengthening wires by +1 in their respective cardinal directions.

[WhiteNinjaZ]

The following shows the difference between Xilinx and VTR:

Xilinx: In green SB, in red CLB