[ODIN] ifdef-endif not recognized properly

[ArashAhmadian]

ifdef-endif seems to not be recongized properly by Odin. The adder circuits located here are syntactically correct however Odin marks the output sum as undriven.

Expected Behaviour

Should synthesize without getting rid of the output sum as it is driven.

Current Behaviour

The output is thought to be undriven and is removed:

home/ahmadi55/vtr-verilog-to-routing/vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/test.v:13:3: 
warning[NETLIST]:  This output is undriven (adder_tree_top^sum~0) and will be removed
    11 | input clk;
    12 | input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
    13 | output [`ADDER_WIDTH  :0] sum;
          ^~~~
    14 | reg    [`ADDER_WIDTH  :0] sum;
    15 |

If the ifdef-endif strucutres are simply removed and the non-blocking statement sum<=sum0 or sum <= sum0_0 are put in the always block, the circuit synthesizes fine.

Steps to Reproduce

1. Attempt to synthesize a circuit under: https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog.
   (e.g. Run ./odin_II -V ../vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_004bits.v from the ODIN_II directory)

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